AD9571ACPZLVD

Overview

The AD9571ACPZLVD is a multioutput clock generator featuring a dedicated PLL core optimized for Ethernet line card applications. It operates from a single 3.3 V supply and accepts a 25 MHz input reference via an external crystal or clock signal. The device generates ten clock outputs: six 25 MHz CMOS, one 33.33 MHz CMOS, one 156.25 MHz differential (LVPECL/LVDS), and two configurable 100 MHz or 125 MHz differential outputs. It utilizes preprogrammed divide ratios and includes an integrated loop filter, eliminating the need for external components. The unit is housed in a 40-lead 6 mm × 6 mm LFCSP package.

Feature Summary

• Fully integrated VCO/PLL core with 0.17 ps rms jitter at 156.25 MHz (1.875 MHz to 20 MHz).
• Ten clock outputs including six 25 MHz CMOS, one 33.33 MHz CMOS, and four differential LVPECL/LVDS signals.
• Preset divide ratios for 156.25 MHz, 125 MHz, 100 MHz, and 33.33 MHz configured via strapping pins.
• Integrated loop filter and crystal oscillator support for a 25 MHz reference input.

Applications

• Ethernet line cards, switches, and routers
• SCSI, SATA, and PCI-express systems
• Low jitter, low phase noise clock generation

Procurement Notes

Verify the specific output format configuration (LVPECL vs. LVDS) required for the target application, as this is factory programmed. Confirm that the design accommodates the 40-lead LFCSP thermal requirements by ensuring the exposed paddle is properly attached to ground for electrical connection and heat dissipation.

Selection Notes

Select this component when a fixed set of Ethernet-specific frequencies is required without digital programming overhead. Ensure the system can provide a stable 25 MHz reference source, either through an external crystal connected to XO pins or a clock signal on REFCLK. Verify power supply stability within the 3.0 V to 3.6 V range to maintain specified jitter performance.

Part Context

The AD9571 belongs to Analog Devices' portfolio of high-performance frequency synthesizers designed for network infrastructure. It replaces discrete PLL and buffer solutions by integrating the VCO, PFD, charge pump, and dividers into a single chip. This integration reduces board space and simplifies the design process for gigabit Ethernet applications.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.