AD9572ACPZLVD

Overview

The AD9572ACPZLVD is a multioutput clock generator with dual PLL cores, optimized for fiber channel line cards including Ethernet interfaces. It provides seven outputs: one LVPECL/LVDS at 156.25 MHz, two LVPECL/LVDS at 106.25 MHz, one LVPECL/LVDS at 100/125 MHz, one CMOS at 33.33 MHz, and one CMOS at 25 MHz. The device operates from a single 3.3 V supply within a −40°C to +85°C temperature range. Jitter performance includes 0.19 ps rms (1.875 MHz to 20 MHz) at 156.25 MHz and 0.22 ps rms (637 kHz to 10 MHz) at 106.25 MHz.

Feature Summary

• Dual fully integrated VCO/PLL cores with preprogrammed feedback and output dividers
• Integrated loop filters eliminating external components
• Choice of LVPECL or LVDS output formats for high-speed signals
• Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz, and 125 MHz

Applications

• Fiber channel line cards, switches, and routers
• Gigabit Ethernet support
• PCIe support
• Low jitter, low phase noise clock generation

Procurement Notes

Verify the package type is the 40-lead, 6 mm × 6 mm LFCSP. Confirm the operating voltage is 3.3 V and the temperature range covers −40°C to +85°C. Ensure the specific ordering suffix matches the required tape-and-reel or tray packaging configuration.

Selection Notes

Select this component when designing fiber channel or Gigabit Ethernet systems requiring multiple synchronized clock frequencies. The preset divide ratios simplify design by removing the need for programmable logic or external loop filter calculations. Verify that the required output formats (LVPECL or LVDS) align with the downstream receiver inputs.

Part Context

The AD9572 is part of Analog Devices' clock generator portfolio designed for networking applications. It integrates crystal oscillators, PLLs, and output buffers into a single chip, reducing board space and design time compared to discrete solutions.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.