AD9572ACPZPEC-R7

Overview

The AD9572ACPZPEC-R7 is a multioutput clock generator with dual VCO/PLL cores, optimized for fiber channel applications. It provides seven outputs: one 156.25 MHz, two 106.25 MHz, one 100/125 MHz, one 33.33 MHz CMOS, and one 25 MHz copy. The device operates from a single 3.3 V supply within a −40°C to +85°C range. Jitter performance includes 0.19 ps rms (1.875 MHz–20 MHz) at 156.25 MHz LVDS and 0.22 ps rms (0.637 MHz–10 MHz) at 106.25 MHz LVDS. Outputs support LVPECL or LVDS formats via strapping pins.

Feature Summary

• Dual integrated PLL cores with preprogrammed feedback and output dividers
• Integrated loop filters and LDOs eliminate external components
• Configurable LVPECL or LVDS output formats via FREQSEL pin
• Low jitter performance: 0.19 ps rms at 156.25 MHz (1.875 MHz–20 MHz)

Applications

• Fiber channel line cards
• Fiber channel switches and routers
• Gigabit Ethernet and PCIe support

Procurement Notes

Verify the datasheet revision B specifications against the specific manufacturing lot. Confirm that the exposed paddle on the 40-lead LFCSP package is properly grounded for thermal and electrical functionality. Ensure the input reference frequency matches the required 25 MHz specification.

Selection Notes

Select this component when designing fiber channel systems requiring low phase noise without external loop filter tuning. Verify that the available output frequencies (156.25 MHz, 106.25 MHz, 100/125 MHz) align with the target network interface requirements.

Part Context

This part belongs to the AD9572 series of clock generators. The suffix 'PEC' indicates the lead-free LFCSP-40 package variant, while '-R7' denotes the reel packaging format used for surface-mount assembly.

Replacement Considerations

Public confirmed substitute part numbers are not provided in the source material.

FAQ

What determines the output format?

The output format (LVPECL or LVDS) is selected using the FREQSEL pin strapping configuration.

How is the crystal oscillator configured?

An external 25 MHz crystal must be connected between the XO pins (Pins 6 and 7). The internal oscillator circuit requires no additional tuning components.

What is the power dissipation difference between formats?

Power dissipation is approximately 0.71 W for LVDS operation and 1.07 W for LVPECL operation.