AD9572ACPZPEC

Overview

The AD9572ACPZPEC is a multioutput clock generator with dual PLL cores, designed for fiber channel applications. It operates from a single 3.3 V supply and accepts a 25 MHz input reference via crystal or clock. The device generates seven outputs: one 156.25 MHz, two 106.25 MHz, one selectable 100/125 MHz, one 33.33 MHz CMOS, and one 25 MHz copy. Outputs support LVPECL or LVDS formats. Jitter performance includes 0.19 ps rms (1.875 MHz to 20 MHz) at 156.25 MHz and 0.42 ps rms (12 kHz to 20 MHz) at 125 MHz. Power dissipation is 0.71 W in LVDS mode and 1.07 W in LVPECL mode.

Feature Summary

• Dual integrated VCO/PLL cores with preprogrammed divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz, and 125 MHz.
• Configurable LVPECL or LVDS output formats selected via strapping pins.
• Integrated loop filters and LDOs eliminate external components.
• Low jitter performance: 0.22 ps rms at 106.25 MHz (0.637 MHz to 10 MHz).

Applications

• Fiber channel line cards
• Fiber channel switches and routers
• Gigabit Ethernet and PCIe support

Procurement Notes

Verify the component against the official Analog Devices datasheet Rev. B. Confirm that the package matches the 40-lead, 6 mm × 6 mm LFCSP specification. Ensure the operating temperature range of −40°C to +85°C aligns with system requirements. Cross-reference pin assignments and electrical parameters directly with the manufacturer's documentation.

Selection Notes

Select this component when a fixed-frequency clock solution for fiber channel is required without processor intervention. The AD9572 supports both LVPECL and LVDS outputs, allowing flexibility in interface selection. Verify that the 25 MHz reference input requirement fits the system design. Consider power dissipation limits, as LVPECL operation consumes up to 1.07 W compared to 0.71 W for LVDS.

Part Context

The AD9572 is part of Analog Devices' portfolio of high-performance frequency synthesizers optimized for networking applications. It integrates dual PLL cores, crystal oscillators, and output buffers into a single compact package. This integration reduces board space and design time by removing the need for external loop filters and discrete regulators.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided source material.

FAQ

How are the output frequencies configured?

Output rates are configured via strapping pins (FREQSEL), which select between preset divide ratios such as 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz, and 125 MHz.

What is the maximum input frequency supported?

The AD9572 supports an input crystal or clock frequency of 25 MHz connected to the REFCLK pin.

Does the device require external loop filter components?

No, the AD9572 features integrated loop filters, conserving valuable design time and board space.