ADG2128YCPZ-REEL

Overview

The ADG2128YCPZ-REEL is an analog crosspoint switch array featuring a configuration of eight columns by twelve rows, providing a total of 96 independent bidirectional signal channels. It operates with dual ±5 V or single +12 V supplies and supports standard, fast, and high-speed (3.4 MHz) I²C interfaces. The device utilizes double-buffered input logic for simultaneous updates and includes hardware reset capabilities. Packaged in a 32-lead LFCSP (5 mm × 5 mm), it offers up to 300 MHz bandwidth, maximum on-resistance of 35 Ω, and low quiescent current below 20 µA.

Feature Summary

• I²C-compatible serial interface supporting standard, fast, and high-speed modes
• Double-buffered input logic enabling simultaneous update of multiple switches
• Hardware reset functionality ensuring all switches initialize to the off state
• Bidirectional signal routing with flexible row and column configuration

Applications

• AV switching in television systems
• Automotive infotainment signal routing
• Test equipment and instrumentation front ends
• KVM switching matrices
• Telecommunications PBX systems

Procurement Notes

Verify the specific suffix against official documentation to confirm temperature range and speed options. The Y version indicates an extended operating temperature range up to +125°C. Confirm package type and reel specifications match design requirements before ordering.

Selection Notes

Select this component when a high-density crosspoint matrix is required for signal routing. Ensure the application voltage aligns with the specified dual ±5 V or single +12 V operation. Consider the automotive qualification if the environment exceeds standard industrial temperature limits.

Part Context

This part belongs to the ADG2128 family of CMOS analog crosspoint switches manufactured by Analog Devices. It provides a compact solution for managing complex signal paths in embedded systems without requiring external multiplexers.

Replacement Considerations

Check for -HS variants if higher I²C clock speeds are required. Verify pin compatibility with existing designs when considering alternative manufacturers' crosspoint arrays.

FAQ

How is the slave address determined?

The 7-bit slave address has four hard-coded MSBs set to 1110. The three LSBs are configured via the A0, A1, and A2 pins, allowing up to eight devices on one bus.

What is the function of the LDSW command?

The Load Switch (LDSW) command allows simultaneous updating of multiple switches. In latched mode, data is stored but not applied until LDSW is asserted high.

Does the device support readback?

Yes, the ADG2128 supports reading back the status of any switch channel in standard and fast I²C modes for system debugging.