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Product Detailed Parameters
- Description:IC RECOVER CLOCK/DATA 48-LFCSP
- Series:-
- PLL:Yes
- Mfr:Analog Devices Inc.
- Main Purpose:SONET/SDH, STM
- Input:CML
- Output:CML
- Number of Circuits:-
- Ratio - Input:Output:1:02
- Differential - Input:Output:Yes/Yes
- Frequency - Max:2.66GHz
- Voltage - Supply:3V ~ 3.6V
- Operating Temperature:-40°C ~ 85°C
- Mounting Type:Surface Mount
- Package / Case:48-WFQFN Exposed Pad, CSP
- Supplier Device Package:48-LFCSP (7x7)
- Grade:-
- Qualification:-
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Overview
The ADN2811ACP-CML is a continuous-rate clock and data recovery IC designed for SONET OC-48 and SDH STM-16 applications. It operates at data rates of 2.48 Gbps (OC-48) and 2.66 Gbps (OC-48 FEC). The device features CML differential inputs and outputs, with a single-supply voltage range of 3 V to 3.6 V. Typical power consumption is 540 mW. It includes a quantizer sensitivity of 4 mV typical, adjustable slice levels, and loss of signal detection. The component is housed in a 7 mm × 7 mm, 48-lead LFCSP package.
Feature Summary
- Meets SONET jitter transfer, generation, and tolerance requirements.
- Supports native OC-48 and 15/14 FEC wrapper rates without reference clock changes.
- Patented delay-locked and phase-locked loop architecture minimizes jitter peaking.
- Single reference clock frequency accommodates both native SONET and wrapper rates.
Applications
- SONET OC-48 and SDH STM-16 systems.
- 15/14 FEC WDM transponders.
- Regenerators and repeaters.
- Backplane applications.
Procurement Notes
Verify the specific ordering suffix against the manufacturer's current documentation to confirm pinout compatibility and electrical specifications. Ensure that the supply voltage and thermal management requirements align with the target PCB design. Confirm availability status through authorized distributors as stock levels may vary.
Selection Notes
Select this component for high-speed optical receiver front ends requiring low jitter performance. Ensure the system supports CML signaling for both input and output interfaces. Verify that the reference clock frequency options (19.44 MHz to 155.52 MHz) match the system architecture. Consider the 48-lead LFCSP package size for board space constraints.
Part Context
The ADN2811 belongs to Analog Devices' family of clock and data recovery solutions. It is specifically engineered for optical communication standards, providing integrated limiting amplifier and CDR functions. This reduces the need for external components in fiber optic receiver designs.
Replacement Considerations
Check for direct pin-to-pin replacements within the ADN281x series. Verify that any substitute maintains the same CML I/O levels and package dimensions. Ensure the replacement meets identical SONET jitter specifications.
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