ADN2813ACPZ-500RL7

Overview

The ADN2813ACPZ-500RL7 is a clock and data recovery (CDR) integrated circuit manufactured by Analog Devices Inc. It supports continuous serial data rates from 10 Mb/s to 1.25 Gb/s without requiring an external reference clock or programming. The device integrates a limiting amplifier, quantizer, and CDR loop filter within a 32-lead LFCSP package. It operates on a single 3.3 V supply with typical power consumption of 450 mW. Key features include adjustable slice levels, loss-of-signal detection, and compliance with SONET jitter requirements.

Feature Summary

• Supports data rates from 10 Mb/s to 1.25 Gb/s
• Exceeds SONET OC-1/OC-3/OC-12 jitter transfer, generation, and tolerance specifications
• Integrated limiting amplifier with 3.3 mV typical sensitivity
• Adjustable loss-of-signal (LOS) detector range from 2.3 mV to 19 mV

Applications

• SONET OC-1, OC-3, and OC-12 systems
• Fibre Channel and Gigabit Ethernet (GbE)
• WDM transponders and regenerators
• Broadband cross-connects and routers

Procurement Notes

Verify the specific ordering suffix -500RL7 against the manufacturer's current datasheet to confirm packaging details such as reel size and tape width. Confirm that the LFCSP-32 package variant matches the required PCB footprint dimensions and thermal pad connectivity for proper heat dissipation.

Selection Notes

Select this component when designing fiber optic receivers requiring high-speed clock recovery up to 1.25 Gb/s. Ensure the application provides a stable 3.3 V supply and allows for the connection of a PIN diode and TIA preamplifier if implementing a complete receiver front-end. Verify that the I2C interface capabilities are sufficient for any required configuration adjustments.

Part Context

This part belongs to the ADN2813 series of clock and data recovery ICs. It is designed to replace older discrete solutions by integrating the limiting amplifier and CDR functions into a single compact package. The device is suitable for applications demanding low jitter performance and automatic rate adaptation across various optical communication standards.

Replacement Considerations

Check for updated revisions of the ADN2813 series. Verify pin compatibility if substituting with other CDR devices in the same family. Ensure that alternative components support the required 1.25 Gb/s data rate and meet the same SONET jitter specifications.

FAQ

Does the ADN2813 require an external reference clock?

No, the ADN2813 automatically locks to input data rates without needing an external reference clock or programming.

What is the typical sensitivity of the quantizer?

The typical quantizer sensitivity is 3.3 mV p-p for a BER of 1 × 10^-10.

How is the loss-of-signal threshold adjusted?

The LOS threshold is user-adjustable via an external resistor connected to the THRADJ pin, allowing a detect range from 2.3 mV to 19 mV.