AK8135C

Overview

The AK8135C is a low-power multiclock generator with a built-in Voltage Controlled Frequency Oscillator (VCFO). It generates seven distinct clock outputs from a single 24.576MHz crystal input. The device provides frequencies including 24.576MHz, 24.99972MHz, 33.332965MHz, 74.1758/74.250MHz, 36.864MHz, and three 27.000MHz reference clocks. The VCFO allows frequency adjustment of ±96ppm via the VIN pin to synchronize with external systems. It operates on a 3.0V to 3.6V supply with typical current consumption of 26mA.

Feature Summary

• Generates seven output clocks from one 24.576MHz crystal source
• Built-in VCFO with ±96ppm pull range for system synchronization
• Low period jitter performance ranging from 150ps to 300ps depending on output
• Configurable output enablement via REF0PD and REF1PD control pins

Applications

• HDD, DVD, and BD Recorders
• Digital Television (DTV)
• Set-Top Boxes (STBs)

Procurement Notes

Verify the package type is 30-pin VSOP and confirm the operating temperature range covers -20°C to +85°C. Ensure the design supports a 3.3V nominal supply voltage within the 3.0V to 3.6V specification limits. Check that the PCB layout accommodates the required decoupling capacitors near each VDD pin.

Selection Notes

Select this component when a single crystal input must drive multiple asynchronous clock domains. The VCFO feature is essential if the system requires fine frequency tuning to match an external master clock. Verify that the specific output frequencies (e.g., 24.99972MHz vs 25.000MHz) align with the target application's timing requirements.

Part Context

The AK8135C belongs to AKM’s low-power multi-clock generator family. It is designed for consumer electronics requiring high-performance clocking with minimal power draw. The device integrates both PLL and VCFO circuitries derived from AKM's clock technology expertise.

Replacement Considerations

No public confirmed substitute part numbers are available in the provided documentation.

FAQ

How is the CLK4 output frequency selected?

The CLK4 output frequency is determined by the HDSEL pin. When HDSEL is Low, it outputs 74.1758MHz; when High, it outputs 74.250MHz. This function is only active when the REF0PD pin is High.

What is the purpose of the VIN pin?

The VIN pin accepts a DC control voltage to adjust the VCFO frequency. This allows the 27MHz reference outputs (REF1-3) to be pulled by up to ±96ppm for synchronization purposes.

Can individual clock outputs be disabled?

Yes. The REF0PD pin controls the CLK4 and REF2 outputs, while the REF1PD pin controls the CLK5 and REF3 outputs. Setting these pins Low disables the respective outputs and powers down the associated PLLs.