AT17C010-10JI

Overview

The AT17C010-10JI is a 1-Mbit (1,048,576 x 1-bit) serial EEPROM configurator designed for FPGA configuration. It operates at 5V with an industrial temperature range of -40°C to +85°C and supports a maximum clock frequency of 15 MHz. The device features a simple serial interface compatible with SRAM-based FPGAs, including Xilinx and Altera devices. It offers in-system programming via a 2-wire bus, programmable reset polarity, and a system-friendly READY pin. Available in 20-lead PLCC packages, it provides low-power standby mode and cascading capabilities for higher-density arrays.

Feature Summary

• Supports In-System Programming via 2-wire bus
• Features programmable reset polarity and system-friendly READY pin
• Enables cascading for additional configurations or higher-density arrays
• Compatible with major FPGA architectures including Xilinx and Altera

Applications

• Configuration memory for Field Programmable Gate Arrays (FPGAs)
• Drop-in replacement for XC17/ATT17 PROMs in Xilinx/Lucent applications
• In-System Programming of FPGA configuration data

Procurement Notes

Verify the specific ordering suffix 'JI' corresponds to the Industrial temperature range (-40°C to +85°C) and 20-lead PLCC package as defined in the manufacturer's ordering guide. Confirm that the 5V supply voltage requirement aligns with your system design, as this is the C-series variant distinct from the LV-series. Ensure compatibility with existing FPGA master serial mode interfaces before procurement.

Selection Notes

Select this component when a 1-Mbit capacity is required for SRAM-based FPGA configuration. The industrial grade rating makes it suitable for environments requiring operation down to -40°C. Consider the 20-lead PLCC package if board space allows for larger footprints compared to the 8-lead options. Verify that the 5V logic levels match the FPGA's input requirements without additional level shifting.

Part Context

This part belongs to the AT17 Series high-density FPGA Configuration EEPROMs, also known as Configurators. The series includes 512-Kbit and 1-Mbit variants in both 5V (C-series) and 3.3V (LV-series). These devices are designed to simplify FPGA initialization by storing configuration programs and interfacing directly with FPGA control signals like CCLK and CE.

Replacement Considerations

AT17C010-10JC

FAQ

How does the READY pin function during power-up?

The READY pin is driven Low during the power-up reset cycle and released (tri-stated) when the power-up is complete, indicating a good power level to the FPGA.

Can multiple AT17C010 devices be used together?

Yes, the devices support cascading. The CEO output of one device drives the CE input of the next, allowing for additional memory capacity or configuration of higher-density FPGA arrays.