AT17C002-10CI

Overview

The AT17C002-10CI is a 2-megabit (2,097,152 x 1-bit) serial configuration EEPROM designed for programming Field Programmable Gate Arrays. It operates at a nominal 5V supply voltage and supports an industrial temperature range of -40°C to +85°C. The device utilizes a simple serial interface compatible with FPGA Master Serial Mode, allowing direct connection without external controllers. It features in-system programmability via a 2-wire bus and includes a system-friendly READY pin to indicate power-up completion.

Feature Summary

• EE reprogrammable memory architecture specifically engineered to store configuration programs for SRAM-based FPGAs
• In-system programmability enabled through a standard 2-wire serial bus interface
• Configurable reset polarity logic stored within the EEPROM bytes to match FPGA requirements
• Integrated READY output pin that signals valid power levels during the initialization sequence

Applications

• Configuration of Xilinx XC3000, XC4000, XC5200, Spartan, and Virtex series FPGAs
• Programming Altera FLEX and APEX family devices
• Initialization of Lucent ORCA and Atmel AT6000, AT40K, and AT94K FPGA architectures
• Daisy-chained cascading configurations for high-density FPGA arrays

Procurement Notes

Verify the specific package type required for the design, as the CI suffix denotes the Industrial temperature grade but does not specify the physical footprint. Confirm compatibility with existing FPGA master serial mode timing requirements. Ensure the design accounts for the 5V nominal supply voltage constraints defined in the absolute maximum ratings. Cross-reference the ordering code against current manufacturer documentation to confirm availability status.

Selection Notes

Select this component when a non-volatile solution is required for FPGA configuration data storage. It serves as a drop-in replacement for legacy PROMs such as the XC17 or ATT17 series. Consider the cascading capability if the target FPGA requires more than 2 megabits of configuration data. Verify that the target FPGA supports the serial master mode protocol utilized by this configurator.

Part Context

This part belongs to the AT17 Series of FPGA Configuration EEPROMs manufactured by Atmel, now Microchip Technology. The series provides cost-effective memory solutions for programming field programmable gate arrays. The AT17C002 variant specifically offers 2-megabit density, while the LV version supports lower voltage operation. The family is designed for seamless integration with various FPGA architectures from major manufacturers.

Replacement Considerations

AT17LV002-10CI

FAQ

How is the reset polarity configured on the AT17C002?

The user can program the reset polarity to be either active low or active high by writing to four specific EEPROM bytes within the device.

What is the function of the CEO pin in a multi-device setup?

The Chip Enable Output (CEO) goes low when the address counter reaches its maximum value, enabling the next configurator in a daisy-chain sequence.

Can this device be programmed after installation on the board?

Yes, the device supports In-System Programming (ISP) via a 2-wire serial bus when the SER_EN pin is driven low.