AT17C128-10NI

Overview

The AT17C128-10NI is an industrial-grade, 5V FPGA configuration EEPROM providing 131,072 x 1-bit serial memory. It operates within a temperature range of -40°C to +85°C and supports a maximum clock frequency of 12.5 MHz in standalone mode. The device utilizes a simple serial interface for configuration and features programmable reset polarity. It is available in an 8-pin SOIC package.

Feature Summary

• Designed specifically for storing configuration programs for Field Programmable Gate Arrays (FPGAs)
• Supports In-System Programming via a 2-wire serial bus
• Features a cascadable read-back capability to support additional configurations or higher-density arrays
• Includes a low-power standby mode with active current consumption under 150 µA

Applications

• Configuration of Atmel AT6000 and AT40K FPGAs
• Configuration of Altera FLEX devices
• Configuration of Xilinx XC3000, XC4000, XC5200, and SPARTAN FPGAs

Procurement Notes

Verify the specific suffix 'NI' corresponds to the Industrial temperature range (-40°C to +85°C) and 8-lead SOIC package as defined in the ordering information. Confirm that the design requires the 5V nominal supply voltage characteristic of the 'C' series rather than the 3.3V LV series. Ensure compatibility with standard industry programmers or the ATDH2200E kit for programming operations.

Selection Notes

Select this component when configuring FPGAs requiring 128K-bit capacity in industrial environments. Choose the NI suffix for surface-mount applications needing the 8-lead SOIC form factor. Consider the cascading capabilities if multiple smaller FPGAs require configuration from a single chain, noting that the CEO output facilitates daisy-chaining with other 128K or 256K devices.

Part Context

This part belongs to the AT17C/LV65/128/256 family of FPGA Configuration EEPROMs manufactured by Atmel, now Microchip Technology. These configurators provide cost-effective memory solutions for establishing FPGA logic functions and interconnections upon power-up or command. The family includes 64K, 128K, and 256K density options in both 5V and 3.3V variants.

Replacement Considerations

AT17LV128-10NI

FAQ

How does the device handle system resets during configuration?

The RESET/OE input can be driven by the FPGA's reset pin. A Low level on RESET/OE clears the Configurator's internal address pointer, allowing reconfiguration to start from the beginning.

What is the function of the CEO pin?

The Chip Enable Output (CEO) is asserted Low on the clock cycle following the last bit read. It enables cascading by signaling the next EEPROM in the chain to begin data transmission.