AT17C128-10PC

Overview

The AT17C128-10PC is a 131,072 x 1-bit serial configuration memory device designed for Field Programmable Gate Arrays (FPGAs). It operates at a nominal 5V supply voltage with a maximum clock frequency of 12.5 MHz in standalone mode and 8 MHz when cascaded. The component utilizes a low-power CMOS EEPROM process and features a simple serial interface compatible with FPGA Master Serial Mode. It supports in-system programming via a 2-wire bus and includes programmable reset polarity and write protection capabilities.

Feature Summary

• Designed to store configuration programs for FPGAs such as Xilinx XC4000 and Altera FLEX devices
• Supports in-system programming through a 2-wire serial bus interface
• Features programmable reset polarity and hardware/software data protection mechanisms
• Enables cascading read-back functionality to support multiple configurations or higher-density arrays

Applications

• Configuration of Xilinx XC3000, XC4000, and XC5200 FPGAs
• Configuration of Altera FLEX and Lucent ORCA FPGAs
• Storage of configuration programs for Atmel AT6000 and AT40K devices

Procurement Notes

Verify the package type corresponds to the 8-pin Plastic Dual Inline Package (PDIP) designation. Confirm the operating temperature range matches commercial requirements (0°C to +70°C). Ensure the supply voltage aligns with the 5V ± 5% specification for the AT17C series. Check for authenticity markers consistent with Microchip/Atmel manufacturing standards.

Selection Notes

Select this component for applications requiring non-volatile storage of FPGA bitstreams. It is suitable for designs utilizing FPGAs that support Master Serial Mode configuration. Consider the 128Kbit density for single or multiple smaller FPGA configurations. Verify compatibility with the target FPGA's clock speed and voltage levels before integration.

Part Context

This part belongs to the AT17 Series of FPGA Configuration EEPROMs, which also includes the AT17C65 and AT17C256 variants. The series provides cost-effective configurators for various FPGA families. The 'C' suffix indicates 5V operation, while 'LV' variants exist for 3.3V systems. The 'PC' suffix specifically denotes the 8-pin PDIP package with commercial temperature rating.

Replacement Considerations

AT17C128-10NC

FAQ

How is the reset polarity configured?

The reset polarity is programmable as either active High or active Low by writing to a special EEPROM byte during the programming mode.

What is the function of the CEO pin?

The Chip Enable Output (CEO) pin asserts Low after the last bit is read from the memory, enabling the connection of additional configurators in a cascade chain.