AT17C256-10PI

Overview

The AT17C256-10PI is a 256K-bit (262,144 x 1-bit) serial EEPROM configurator designed for Field Programmable Gate Arrays. It operates at a nominal 5V supply voltage and supports an industrial temperature range of -40°C to +85°C. The device features a simple serial interface compatible with FPGA Master Serial Mode, utilizing a CLK input driven by the FPGA's CCLK output. It includes programmable reset polarity, write protection capabilities, and cascading support via a CEO output for expanded memory configurations.

Feature Summary

• Designed specifically as a configuration memory source for FPGA devices in Master Serial Mode
• Supports cascading connections to configure multiple FPGAs or larger arrays using the CEO output signal
• Features programmable reset polarity to adapt to different system reset requirements
• Includes internal write-protection mechanisms accessible during programming mode

Applications

• Configuration of Atmel AT6000 and AT40K series FPGAs
• Configuration of Altera FLEX devices
• Configuration of Xilinx XC3000, XC4000, XC5200, and SPARTAN FPGAs
• Configuration of Lucent ORCA and Motorola MPA1000 FPGAs

Procurement Notes

Verify that the specific part number corresponds to the 5V commercial/industrial variant rather than the 3.3V LV version. Confirm the package type matches the required PCB footprint, as this model utilizes an 8-pin PDIP format. Ensure compatibility with the target FPGA's clock frequency specifications before finalizing procurement decisions.

Selection Notes

Select this component when configuring FPGAs requiring up to 256K bits of non-volatile storage. Choose the 'C' suffix variant for 5V systems and the 'LV' variant for 3.3V systems. Consider the 'I' suffix for industrial temperature environments. Evaluate cascading needs; if more than 256K bits are required, utilize the CEO pin to chain additional devices.

Part Context

This device belongs to the low-density AT17 Series of FPGA Configuration EEPROMs. The family includes 64K, 128K, and 256K density options. The 'C' designation indicates standard 5V operation, while 'LV' denotes 3.3V operation. The 'PI' suffix specifies the Industrial temperature grade and 8-pin Plastic Dual Inline Package.

Replacement Considerations

AT17C256-10PC

FAQ

How is the reset polarity configured?

The reset polarity is programmable within the EEPROM itself. Users can set it to be active High or active Low depending on the specific connection method used between the FPGA CON pin and the EEPROM inputs.

Can this device be used in a cascade chain?

Yes, the AT17C256 supports cascading. The CEO output asserts Low after the last bit is read, enabling the next EEPROM in the chain to drive its data output.

What is the function of the SER_EN pin?

The SER_EN pin enables the 2-wire serial programming mode when pulled Low. During normal FPGA loading operations, this pin must be held High.