AT17C65-10NI

Overview

The AT17C65-10NI is a 64K-bit (65,536 x 1-bit) serial EEPROM configurator designed for Field Programmable Gate Arrays. It operates at 5V nominal voltage within an industrial temperature range of -40°C to +85°C. The device utilizes a simple serial interface with a maximum clock frequency of 12.5 MHz and supports in-system programming via a 2-wire bus. It is housed in an 8-pin Plastic Dual Inline Package (PDIP).

Feature Summary

• Designed specifically to store configuration programs for FPGA devices.
• Supports In-System Programming through a 2-wire serial bus interface.
• Features programmable reset polarity for flexible system integration.
• Includes a write-protection mechanism within the programming mode.

Applications

• Configuration memory for Atmel AT6000 and AT40K FPGAs.
• Configuration memory for Altera FLEX devices.
• Configuration memory for Xilinx XC3000, XC4000, XC5200, and SPARTAN FPGAs.

Procurement Notes

Verify that the component matches the specific industrial temperature grade (-40°C to +85°C) required for your application environment. Confirm the package type corresponds to the 8-pin PDIP variant as indicated by the ordering suffix. Ensure compatibility with standard industry programmers or the specified Atmel programming kit for initial configuration.

Selection Notes

Select this part when a cost-effective, low-power solution is needed for configuring smaller FPGA arrays. It is suitable for systems requiring a simple serial interface to SRAM-based FPGAs. Consider the AT17LV series if a 3.3V supply voltage is mandatory instead of the standard 5V operation provided by the AT17C series.

Part Context

This component belongs to the AT17 Series of low-density FPGA Configuration EEPROMs. The family includes variants with 64K, 128K, and 256K bit densities. While the 128K and 256K versions support cascading for larger configurations, the 64K version is typically used as a standalone device or at the end of a cascade chain.

Replacement Considerations

AT17C65-10PC

FAQ

Can the AT17C65 be used in a cascaded configuration?

No, the AT17C65 cannot drive the Chip Enable Output (CEO) signal required for cascading. It can only be used as a standalone device or at the end of a cascade chain initiated by AT17C128 or AT17C256 devices.

How is the reset polarity configured?

The reset polarity is programmable by the user. A special EEPROM byte can be programmed to set the RESET/OE input logic polarity to either active High or active Low using an industry-standard programmer.