AT17F080-30BJC

Overview

The AT17F080-30BJC is an 8-Mbit serial configuration memory device designed for Field Programmable Gate Arrays (FPGAs). It operates at a nominal 3.3V supply voltage with 5V tolerant I/O pins and supports in-system programming via a 2-wire bus. The device features fast serial download speeds up to 33 MHz, low-power standby mode, and compatibility with various FPGA families including Xilinx and Altera. It is housed in a 44-lead Plastic J-leaded Chip Carrier (PLCC) package.

Feature Summary

• Designed specifically for storing configuration programs for SRAM-based FPGAs
• Supports In-System Programming (ISP) using a simple 2-wire serial bus interface
• Features cascading capability to support multiple configurations or higher-density arrays
• Includes page select inputs allowing storage of multiple configuration bitstreams from a single device

Applications

• Configuration of Xilinx XC3000, XC4000, XC5200, Spartan, and Virtex FPGAs
• Configuration of Altera FLEX and APEX devices
• Configuration of Atmel AT40K and AT94K devices
• Configuration of Lucent ORCA and Motorola MPA1000 FPGAs

Procurement Notes

Verify the specific ordering suffix 'BJC' corresponds to the 44-lead PLCC package and commercial temperature range as defined in the official datasheet. Confirm that the component is sourced from authorized distributors to ensure authenticity, as this is a legacy configuration memory part originally manufactured by Atmel Corporation before its acquisition by Microchip Technology.

Selection Notes

Select this component when an 8-Mbit capacity is required for FPGA configuration. Ensure the design utilizes a 44-lead PLCC footprint. Verify that the target FPGA supports Master Serial mode and is compatible with the AT17F series configurators. Consider the 3.3V operation and 5V tolerance if interfacing with mixed-voltage logic systems.

Part Context

This part belongs to the AT17F Series of In-System Programmable Configuration PROMs. Originally developed by Atmel Corporation, these devices are now managed under Microchip Technology's portfolio. The series provides cost-effective configuration solutions for SRAM-based FPGAs, offering flexibility through ISP capabilities and compatibility with industry-standard programmers.

Replacement Considerations

AT17F080-30TQC (44-lead TQFP package)

FAQ

How does the device handle cascading for larger configuration memories?

The CEO output of one device connects to the CE input of the next configurator in the chain. When the first device finishes reading data, it drives CEO Low, enabling the second device's DATA output.

What is the function of the PAGE_EN pin?

When PAGE_EN is High, the address space is partitioned into four equal pages, allowing users to store and retrieve multiple configuration bitstreams from a single device using the PAGESEL inputs.