AT17C128-10NC

Overview

The AT17C128-10NC is a 131,072 x 1-bit serial EEPROM designed for FPGA configuration. It operates at 5V nominal and supports industrial temperature ranges from -40°C to +85°C. The device features a simple 2-wire serial interface for in-system programming and connects via CLK, DATA, CE, and RESET/OE pins. It includes programmable reset polarity and write protection mechanisms.

Feature Summary

• Designed specifically for storing configuration programs for Field Programmable Gate Arrays (FPGAs)
• Supports in-system programming via a 2-wire serial bus
• Features programmable reset polarity and internal write-protection mechanisms

Applications

• Configuration of Atmel AT6000 and AT40K FPGAs
• Configuration of Altera FLEX devices
• Configuration of Xilinx XC3000, XC4000, and SPARTAN FPGAs

Procurement Notes

Verify the specific package type required, as the NC suffix indicates an 8-pin SOIC package. Confirm that the 5V operating voltage aligns with the target system design, distinguishing it from the LV series which operates at 3.3V. Ensure compatibility with existing FPGA master serial mode requirements before procurement.

Selection Notes

Select this component when a 128K-bit capacity is needed for FPGA configuration in industrial environments. It is suitable for designs requiring 5V logic levels and simple serial interfacing. Consider cascading capabilities if larger memory arrays are required for multiple or high-density FPGAs.

Part Context

This part belongs to the AT17C/LV65/128/256 family of FPGA Configuration EEPROMs. These devices provide cost-effective configuration memory solutions. The AT17C series specifically denotes the 5V version, while the AT17LV series offers 3.3V operation. They are compatible with various industry-standard FPGA families.

Replacement Considerations

AT17C128-10PC

FAQ

Can the AT17C128-10NC be used with 3.3V FPGAs?

No, the AT17C128-10NC is a 5V device. For 3.3V applications, the AT17LV128-10NC should be used.

What is the function of the CEO pin?

The CEO pin is asserted Low on the clock cycle following the last bit read, enabling cascading of multiple EEPROMs for larger configuration memories.