AT17LV002-10SI

Overview

The AT17LV002-10SI is a 2-Mbit serial EEPROM designed for FPGA configuration. It operates at 3.3V (±10%) and 5.0V (±5%). The device supports in-system programming via a two-wire bus and features a simple interface to SRAM FPGAs. It includes programmable reset polarity, cascading capability with CEO output, and low-power standby mode. Endurance is rated at 100,000 write cycles, with data retention of 90 years at 85°C. It is available in the 20-lead SOIC package.

Feature Summary

• Designed specifically to store configuration programs for Field Programmable Gate Arrays (FPGAs).
• Supports In-System Programming (ISP) via a Two-Wire Serial Bus.
• Features a cascadable read-back mechanism using the Chip Enable Output (CEO) pin.
• Allows user-programmable reset polarity through four EEPROM bytes.

Applications

• Configuration memory for Xilinx XC3000, XC4000, XC5200, Spartan, and Virtex FPGAs.
• Configuration memory for Altera FLEX and APEX devices.
• Configuration memory for Atmel AT6000, AT40K, and AT94K devices.
• Cascaded configurations requiring higher-density arrays or additional configurators.

Procurement Notes

Verify that the ordering suffix 'SI' corresponds to the 20-lead Small Outline Integrated Circuit (SOIC) package as specified in the datasheet. Confirm the industrial temperature range (-40°C to +85°C) matches the application requirements. Ensure compatibility with the target FPGA's master serial mode interface signals. Check for RoHS compliance if lead-free assembly is required.

Selection Notes

Select this component when a 2-Mbit capacity is required for FPGA configuration. The 20-lead SOIC package is suitable for surface-mount applications where space allows. Consider the cascading feature if multiple FPGAs need configuration from a single chain. Verify voltage supply compatibility with both 3.3V and 5.0V systems.

Part Context

The AT17LV002-10SI belongs to the AT17LV series of FPGA Configuration EEPROMs manufactured by Microchip Technology (formerly Atmel). This series provides cost-effective, non-volatile memory solutions for loading configuration data into SRAM-based FPGAs upon power-up. The device integrates a serial access procedure to simplify the connection between the memory and the FPGA control signals.

Replacement Considerations

AT17LV002-10SC (Commercial Temperature)

FAQ

How does the AT17LV002-10SI handle cascading with other configuration memories?

The device uses its CEO (Chip Enable Output) pin to daisy-chain with subsequent configurators. When the address counter reaches its maximum value, the CEO goes Low, enabling the CE input of the next device in the chain.

Is the reset polarity fixed or configurable?

The reset polarity is programmable. Users can configure the RESET/OE pin to be active High or active Low by programming four specific EEPROM bytes during the initialization phase.