AT17LV002A-10CU

Overview

The AT17LV002A-10CU is a 2-Mbit (2,097,152 x 1-bit) serial EEPROM configurator designed for FPGA configuration. It supports 3.3V and 5V operation with a 2-wire serial interface. The device operates within a temperature range of -40°C to +85°C and is available in 20-lead PLCC and 32-lead TQFP packages.

Feature Summary

• In-system programmable via a simple 2-wire bus interface
• Supports cascading read-back for higher-density arrays or additional configurations
• Features programmable reset polarity and write protection mechanisms

Applications

• Configuration memory for Altera FLEX and APEX FPGAs
• Configuration memory for Xilinx XC3000, XC4000, XC5200, Spartan, and Virtex FPGAs
• Configuration memory for Atmel AT6000, AT40K, and AT94K devices

Procurement Notes

Verify the package type matches the required design constraints, as the part is available in both 20-lead PLCC and 32-lead TQFP formats. Confirm that the industrial temperature rating (-40°C to +85°C) aligns with the system's environmental specifications. Ensure programming equipment supports the specific 2-wire serial protocol used by this configurator series.

Selection Notes

Select this component when a high-density, low-power non-volatile memory solution is needed for SRAM-based FPGAs. The choice between PLCC and TQFP depends on board space and existing footprint compatibility. Consider cascading capabilities if the target FPGA requires more configuration bits than a single unit provides.

Part Context

This device belongs to the AT17A series of FPGA configuration EEPROMs manufactured by Microchip Technology (formerly Atmel). These configurators provide a cost-effective alternative to parallel PROMs, simplifying the PCB layout by utilizing a serial interface that connects directly to FPGA control signals without requiring an external microcontroller.

Replacement Considerations

AT17LV002A-10PC

FAQ

How does the device handle cascading for larger configurations?

The nCASC output goes Low when the address counter reaches its maximum value, disabling the DATA line driver. This signal typically drives the nCS input of the next configurator in the chain, allowing subsequent devices to clock out data.

Is the reset polarity fixed or configurable?

The reset polarity is programmable. Users can program four EEPROM bytes during the programming phase to set the RESET/OE pin logic polarity to suit specific FPGA requirements.