AT17LV002A-10JC

Overview

The AT17LV002A-10JC is a 2,097,152 x 1-bit serial configuration memory designed for Field Programmable Gate Arrays. It operates on a 3.3V (±10%) or 5.0V (±5% Commercial, ±10% Industrial) supply. The device supports In-System Programming via a 2-wire bus and features a simple interface to SRAM FPGAs. It is available in a 20-lead PLCC package with commercial temperature range operation from 0°C to 70°C.

Feature Summary

• EE Programmable serial memory architecture designed specifically for storing FPGA configuration programs
• In-System Programmable capability via a standard 2-wire bus interface
• Cascadable read-back functionality to support additional configurations or higher-density arrays
• Programmable reset polarity and write-protection mechanisms within the programming mode

Applications

• Configuration of Altera FLEX and APEX FPGAs
• Configuration of Xilinx XC3000, XC4000, XC5200, Spartan, and Virtex FPGAs
• Configuration of Atmel AT6000, AT40K, and AT94K devices
• Configuration of Lucent ORCA FPGAs

Procurement Notes

Verify that the ordering suffix 'JC' corresponds to the 20-lead PLCC package and the Commercial temperature range (0°C to 70°C). Confirm the voltage variant matches the system requirements, as the 'LV' designation indicates low-voltage compatibility but the datasheet specifies distinct voltage tolerances for commercial and industrial grades. Ensure the application utilizes the 2-wire serial interface for ISP if field updates are required.

Selection Notes

Select this component when a 2-Mbit capacity is required for single or cascaded FPGA configuration. It is suitable for designs requiring pin-compatible upgrades across the AT17A series family. Consider the industrial grade variant if operating temperatures extend below 0°C or above 70°C. Verify FPGA compatibility lists for specific device generations before finalizing the design.

Part Context

This part belongs to the AT17A series of FPGA configuration EEPROMs, which provide cost-effective memory solutions for SRAM-based FPGAs. The series includes various densities ranging from 65-Kbit to 4-Mbit. The AT17LV002A specifically targets applications needing high-capacity configuration storage with low-power CMOS technology and simple serial access procedures.

Replacement Considerations

AT17LV002A-10QC (32-lead TQFP package)

FAQ

How is the reset polarity configured?

The user can program the polarity of the RESET/OE pin by writing four specific EEPROM bytes during the programming process.

What is the function of the nCASC pin?

The nCASC pin goes Low when the address counter reaches its maximum value, allowing it to drive the nCS input of the next configurator in a daisy-chain sequence.

Does the device support JTAG programming?

No, the AT17LV002A does not support JTAG programming; it uses a 2-wire serial interface for in-system programming.