AT17LV65A-10JC

Configuration PROMs For FPGAs Overview

The AT17LV65A-10JC is a 64-Kbit (65,536 x 1-bit) serial EEPROM configurator designed for FPGA configuration. It operates at a maximum clock frequency of 10 MHz and supports supply voltages of 3.3V (±10%) or 5.0V (±5% commercial). The device features in-system programmability via a 2-wire bus, low-power standby mode, and high-reliability endurance of 100,000 write cycles with data retention up to 90 years at industrial temperatures.

Configuration PROMs For FPGAs Feature Summary

• In-system programmable via 2-wire serial bus
• Configurable reset polarity for FPGA compatibility
• Cascadable read-back support for higher-density arrays
• Low-power CMOS EEPROM process with standby mode

Configuration PROMs For FPGAs Applications

• Configuration of Altera FLEX and APEX FPGAs
• Configuration of Xilinx XC3000, XC4000, and Spartan devices
• Configuration of Lucent ORCA and Motorola MPA1000 FPGAs
• Emulation of Atmel AT24CXXX serial EEPROMs

Configuration PROMs For FPGAs Procurement Notes

Verify the specific package type required, as the JC suffix denotes a 20-lead PLCC package. Confirm the voltage variant matches the system design, as the 'L' indicates low-voltage operation compatible with both 3.3V and 5V systems. Ensure the programming environment supports the 2-wire serial interface for in-system programming capabilities.

Configuration PROMs For FPGAs Selection Notes

Select this component when configuring SRAM-based FPGAs requiring a simple serial interface. It is suitable for applications needing cascaded memory for larger configuration arrays. Consider the operating temperature range; the 'C' suffix indicates commercial grade (0°C to 70°C), while 'I' is for industrial (-40°C to 85°C). Verify pin compatibility with existing designs if replacing older Atmel or Altera configurators.

Configuration PROMs For FPGAs Part Context

This device belongs to the AT17A series of FPGA configuration EEPROMs. These configurators provide cost-effective storage for FPGA bitstreams. The series includes various densities from 64-Kbit to 2-Mbit, offering pin-compatible packages across the family to simplify design upgrades. The AT17LV65A is the lowest density option in the LV series.

Configuration PROMs For FPGAs Replacement Considerations

AT17LV65A-10PC (PDIP package)

Configuration PROMs For FPGAs FAQ

How is the reset polarity configured?

The polarity of the RESET/OE pin is programmable by writing four specific EEPROM bytes during the programming phase.

Can multiple AT17LV65A devices be used together?

Yes, they are cascadable. The nCASC output of one device connects to the nCS input of the next, allowing daisy-chaining for larger configuration memories.

What is the function of the SER_EN pin?

SER_EN must be held High during normal FPGA loading operations. Bringing it Low enables the 2-wire Serial Programming Mode for in-system programming.