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The AT22LV10-20JI is a low-voltage UV Erasable Programmable Logic Device (PLD) from Microchip Technology, housed in a 28-lead Plastic J-leaded Chip Carrier (PLCC) package. It operates within a supply voltage range of 3.0V to 5.5V and supports an industrial temperature range of -40°C to +85°C. The device features a maximum propagation delay of 20 ns at VCC = 3.0V. It utilizes the familiar 22V10 logic architecture with ten registered outputs, each allocated up to sixteen product terms. Key electrical characteristics include a typical power supply current of 4 mA at 3.6V and CMOS/TTL compatible inputs and outputs.
Verify that the component is the AT22LV10-20JI variant specifically, as ordering suffixes determine package type and temperature range. Confirm the presence of the UV erasure window on the PLCC package if reprogramming capability is required. Ensure handling procedures account for humidity sensitivity and static discharge protection during storage and assembly.
Select this part when an industrial temperature range (-40°C to +85°C) and surface mount PLCC packaging are required. Choose the -20 speed grade for applications needing a maximum 20 ns propagation delay at 3.0V. Consider the AT22LV10L variant only if lower typical power consumption (1 mA vs 4 mA) is critical, noting it shares the same 25 ns speed grade.
This device belongs to the AT22LV10 series of low-voltage UV EPROM PLDs. It is functionally identical to the standard AT22V10 but optimized for 3.0V to 5.5V operation. The 'J' suffix denotes the 28-lead PLCC package, while 'I' indicates the industrial temperature range. It serves as a drop-in replacement for older 5V-only PLDs in designs supporting lower voltage rails.
Public confirmed substitute part numbers: AT22LV10-20JC (Commercial Temp), AT22LV10-20PI (PDIP Package), AT22LV10-20SI (SOIC Package).
Register preload is achieved by applying an 11.5V to 13V signal to pin 8 (on DIPs) or pin 10 (on SMT packages) while pulsing the clock pin high. A VIH level on an I/O pin forces the register high, while a VIL forces it low.
For reliable power-up reset, the VCC rise must be monotonic. All input and feedback setup times must be met before driving the clock pin high, and the clock must remain stable during the power-up reset time (tPR).
The entire fuse array is erased by exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure requires a minimum of 20 minutes using lamps with 12,000 µW/cm² intensity spaced one inch away.