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The C8051F130-GQ is a high-speed mixed-signal System-on-Chip microcontroller from Silicon Labs, featuring an 8051-compatible CIP-51 core with pipelined architecture. It operates at up to 100 MIPS using an internal PLL and includes a 2-cycle 16x16 MAC engine. The device integrates 64 kB of in-system programmable Flash memory and 8448 bytes of internal data RAM. Analog peripherals consist of a 10-bit SAR ADC with programmable throughput up to 100 ksps and two analog comparators. Digital interfaces include hardware SMBus, SPI, and dual UARTs. It supports 64 digital I/O pins in a 100-pin TQFP package.
Verify component authenticity through authorized distribution channels. Confirm that the specific revision matches project requirements, as this family is designated Not Recommended for New Designs. Ensure compatibility with existing PCB footprints and validate firmware against the official datasheet specifications before finalizing procurement orders.
Select this component when a fully integrated mixed-signal solution with high-speed 8051 processing is required. It is suitable for applications needing simultaneous analog conversion and digital communication without external logic. Consider the NRND status for long-term supply chain planning and evaluate alternative families if new product development extends beyond current lifecycle constraints.
This part belongs to the C8051F12x/13x family of 8K ISP Flash MCUs. These devices are designed for cost-sensitive applications demanding high performance and rich peripheral integration. The C8051F130 variant specifically offers 64 kB Flash and a 10-bit ADC, distinguishing it from variants with larger memory or different analog resolutions within the same series.
Consult the official Silicon Labs migration guide for recommended successors. Verify pinout compatibility and peripheral mapping differences when transitioning to newer MCU families to ensure seamless software and hardware integration.