CBTL02043ABQ,115

Overview

The CBTL02043ABQ,115 is a 3.3 V, two differential channel, 2-to-1 multiplexer/demultiplexer switch designed for USB 3.1 and PCI Express Generation 3 applications. It operates within a supply voltage range of 3.0 V to 3.6 V and supports signal switching up to 10 Gbps. The device features a -3 dB bandwidth of 10 GHz, with an on-state resistance maximum of 6 Ohms and a propagation delay of 60 ps. It utilizes a DHVQFN20 package (SOT764-1) with dimensions of 2.5 x 4.5 x 0.85 mm. Operating temperatures range from -40 °C to +85 °C, and it includes a shutdown pin that reduces standby current to less than 1 µA.

Feature Summary

• Supports high-speed signal switching for 10 Gbps applications with minimal attenuation.
• Features low intra-pair skew and inter-pair skew to maintain signal integrity.
• Includes a shutdown pin for power-saving mode with near-zero current consumption.
• Provides ESD tolerance of 2000 V HBM and 1000 V CDM.

Applications

• Routing of high-speed differential signals for PCIe Gen3
• DisplayPort 1.2 signal routing
• USB 3.1 interface expansion
• SATA 6 Gbit/s signal switching

Procurement Notes

Verify the specific ordering suffix ',115' corresponds to the reel packing method as documented in the official NXP data sheet. Confirm the component status is active, as some variants in this family may be marked as no longer manufactured. Ensure the DHVQFN20 package version matches the required PCB footprint specifications for thermal and electrical performance.

Selection Notes

Select the CBTL02043ABQ variant when input and output pins are located on opposite sides of the package, which is suitable for edge connectors with different signal sources on the motherboard. Verify that the application requires a 3.3 V supply and benefits from the low insertion loss characteristics at 4.0 GHz. Ensure the design accommodates the exposed center pad for proper grounding and heat dissipation.

Part Context

This component belongs to the CBTL02043A/B series of multiplexer switches. It is distinct from the CBTL02042ABQ, which is optimized for PCI Express Gen2. The 'A' designation indicates a specific pinout configuration where ports A and B/C are arranged on opposite sides of the DHVQFN20 package, differing from the 'B' variant which has outputs on both sides.

Replacement Considerations

Public confirmed substitute part numbers: None identified in verified documentation.

FAQ

What is the function of the XSD pin?

The XSD pin is a shutdown input. When driven HIGH, it places all channels in a high-impedance state and minimizes supply current consumption. When LOW, the device operates normally.

How does the SEL pin determine the switching path?

The SEL pin selects the operation mode. A LOW level connects Port A to Port B, while a HIGH level connects Port A to Port C.

What is the typical intra-pair skew for this device?

The typical intra-pair skew is 5 ps.