DS90CR485VS/NOPB

Overview

The DS90CR485VS/NOPB is a serializer from the DS90CR485 series manufactured by Texas Instruments. It converts 24 LVCMOS/LVTTL double-edge inputs into 8 Low Voltage Differential Signaling (LVDS) streams, achieving a throughput of up to 6.384 Gbps. The device supports input clock frequencies ranging from 66 MHz to 133 MHz and operates on a 2.5 V supply with 3.3 V tolerant inputs. It features pre-emphasis for cable loading reduction and DC balance to minimize ISI distortion. Packaged in a 100-pin TQFP, it conforms to the TIA/EIA-644-A LVDS standard.

Feature Summary

• Serializes 48 bits of data per clock cycle onto 8 differential LVDS output channels.
• Supports high-speed operation up to 6.384 Gbps with dual-edge data strobing.
• Includes programmable pre-emphasis to mitigate cable loading effects.
• Integrates DC balance functionality to reduce inter-symbol interference.

Applications

• High throughput point-to-point applications requiring EMI reduction.
• Backplane interconnects utilizing differential line impedance.
• Long cable drive applications requiring low distortion eye-patterns.

Procurement Notes

Verify component authenticity through authorized distributors or direct manufacturer channels. Confirm RoHS compliance status and check for moisture sensitivity handling requirements during storage and assembly. Ensure the specific ordering suffix matches the required package and temperature range specifications before finalizing procurement orders.

Selection Notes

Select this serializer when interfacing wide TTL buses to LVDS links to reduce connector size. Ensure the host system provides a clock signal within the 66 MHz to 133 MHz range. Verify that the receiving end utilizes a compatible Channel-Link receiver such as the DS90CR486 or backward-compatible models like the DS90CR484.

Part Context

This component belongs to the DS90CR485 series of serializers designed for high-speed data transmission. It is specifically engineered to work in conjunction with Channel-Link receivers. The device addresses interconnect challenges by reducing pin counts and simplifying PCB routing between host chips and serialization logic.

Replacement Considerations

The DS90CR485 is backward compatible with other Channel-Link receivers such as the DS90CR482 and DS90CR484. When replacing components, ensure the new part maintains compatibility with the existing receiver architecture and meets the same electrical interface standards.

FAQ

How is the pre-emphasis level configured?

Pre-emphasis strength is set via a DC voltage level applied to the PRE pin using an external pull-up resistor to VCC. The resistor value determines the magnitude of dynamic current during data transitions.

What is the function of the TSEN pin?

The TSEN pin reports the presence of a remote termination resistor. It outputs LOW if no termination is detected and HIGH if a 100 Ω termination is present at the far end of the link.

How does the device handle power-down mode?

Asserting the PD pin low activates the power-down function, minimizing power dissipation and shutting down the PLL. The transmitter outputs enter a TRI-STATE condition during this mode.