EP20K1000EFC672-3

EP20K1000EFC672-3

  • Description:IC FPGA 508 I/O 672FBGA
  • Series:APEX-20KE®

SKU:28a8fa41ab95 Category: Brand:

ChipApex WhatsApp

Consult the customer manager about the wholesale price.

consultation hotline:86-132-6715-2157

email:[email protected]
Contact the product manager for consultation. One-stop consultation is available.


Do you want a lower wholesale price? Please send us your inquiry and we will reply immediately.

Submitting!
Submission successful!
Submission failed!
Email error!
Phone number error!

Product Detailed Parameters

  • Description:IC FPGA 508 I/O 672FBGA
  • Series:APEX-20KE®
  • Mfr:Altera
  • Package:Tray
  • Number of LABs/CLBs:3840
  • Number of Logic Elements/Cells:38400
  • Total RAM Bits:327680
  • Number of I/O:508
  • Voltage - Supply:1.71V ~ 1.89V
  • Mounting Type:Surface Mount
  • Operating Temperature:0°C ~ 85°C (TJ)
  • Package / Case:672-BBGA
  • Supplier Device Package:672-FBGA (27x27)
  • Number of Gates:1772000

Download product information

EP20K1000EFC672-3

Overview

The EP20K1000EFC672-3 is a high-density Field Programmable Gate Array (FPGA) belonging to the APEX 20KE family, manufactured by Altera. It features a MultiCore architecture integrating Look-Up Table (LUT) logic, product-term-based macrocells, and Embedded System Blocks (ESBs). The device provides 38,400 Logic Elements (LEs), 2,560 macrocells, and up to 327,680 RAM bits. It operates at a maximum system frequency of 170 MHz with a 1.8 V internal supply voltage (VCCINT). The component utilizes a 672-pin FineLine BGA package and supports MultiVolt I/O standards for interfacing with various voltage levels.

Feature Summary

  • MultiCore architecture combining LUT logic, product-term macrocells, and embedded memory (ESBs)
  • High density with 38,400 LEs, 2,560 macrocells, and 327,680 RAM bits
  • Supports MultiVolt I/O interface for 1.8-V, 2.5-V, 3.3-V, and 5.0-V devices
  • Advanced clock management with four PLLs and ClockLock feature

Applications

  • System-on-a-programmable-chip (SOPC) integration
  • Complex state machines and combinatorial-intensive functions
  • Register-intensive data-path and DSP designs
  • PCI Local Bus Specification compliant interfaces

Procurement Notes

Verify component authenticity through authorized distributors or direct manufacturer channels. Confirm the specific suffix '3N' against official datasheets to ensure correct speed grade and environmental rating. Check for End-of-Life (EOL) status and lead times due to the legacy nature of the APEX 20K family. Ensure handling guidelines for moisture sensitivity are followed during storage and assembly.

Selection Notes

Select this model for applications requiring high logic density and mixed-mode programmability. Compare the 38,400 LE count and 672-pin package against alternative APEX 20K variants like the EP20K600E or EP20K1500E based on resource needs. Consider the 1.8 V core voltage requirement and MultiVolt I/O capabilities when designing power domains. Evaluate the -3 speed grade performance against timing constraints of the target design.

Part Context

The EP20K1000EFC672-3 is part of the APEX 20KE series, an evolution of the original APEX 20K family. It represents one of the highest density options in this lineage, offering significant logic resources before the transition to Stratix and Cyclone families. The 'E' suffix denotes enhanced features such as additional global clocks and broader I/O standard support compared to non-E variants.

Replacement Considerations

No direct public substitute part numbers are confirmed in the provided documentation. Legacy replacements may require migration to newer Intel FPGA families such as Cyclone or Arria, necessitating design adaptation.

EP20K1000EFC672-3EP20K1000EFC672-3

Click on the inquiry