EP20K160EBC356-1N

Overview

The EP20K160EBC356-1N is an APEX 20KE programmable logic device featuring the MultiCore architecture, which integrates look-up table (LUT) logic, product-term logic, and embedded system blocks (ESB). It provides 6,400 logic elements, 40 ESBs, and a maximum of 81,920 RAM bits. The device operates at a 1.8-V internal supply voltage with MultiVolt I/O support for 1.8-V, 2.5-V, 3.3-V, and 5.0-V levels. It includes four phase-locked loops, up to eight global clock signals, and supports LVDS performance up to 840 Mbits per channel. The component is housed in a 356-pin BGA package.

Feature Summary

• MultiCore architecture combining LUT logic, product-term logic, and embedded memory
• 6,400 logic elements and 40 Embedded System Blocks (ESBs)
• 1.8-V core voltage with MultiVolt I/O interface supporting multiple voltage levels
• Four PLLs with ClockLock and ClockBoost features for flexible clock management

Applications

• System-on-a-programmable-chip (SOPC) integration
• Complex state machines and combinatorial-intensive functions
• Register-intensive data-path and DSP designs
• High-speed external memory interfaces including DDR SDRAM

Procurement Notes

Verify the specific -1 speed grade and BC356 package variant against current availability, as this is a legacy Altera device. Confirm RoHS compliance status and moisture sensitivity level requirements for handling and storage prior to procurement.

Selection Notes

Select this device for designs requiring high-density logic with mixed LUT and product-term efficiency. Ensure the design utilizes the 1.8-V core voltage constraints and leverages the MultiVolt I/O capabilities if interfacing with 3.3-V or 5.0-V peripherals.

Part Context

This part belongs to the APEX 20KE family, a superset of the original APEX 20K series. The 'E' suffix denotes enhanced features such as additional global clocks, CAM support, and broader I/O standard compatibility compared to non-E variants.

Replacement Considerations

Direct pin-to-pin replacements are not explicitly listed in the provided documentation. Consider modern Intel/Altera FPGA families for new designs, though architectural differences require schematic and firmware redesign.