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Product Detailed Parameters
- Description：EE PLD, 10NS, 96-CELL PQFP128
- Series：*
- Mfr：Lattice Semiconductor Corporation
- Package：Bulk
- Programmable Type：-
- Delay Time tpd(1) Max：-
- Voltage Supply - Internal：-
- Number of Macrocells：-
- Number of I/O：-
- Operating Temperature：-
- Mounting Type：-
- Package / Case：-
- Supplier Device Package：-
- Number of Gates：-
- Number of Logic Elements/Blocks：-
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Overview
The ISPLSI-2096-125LQ is an Electrically Erasable Programmable Logic Device (EE PLD) manufactured by Lattice Semiconductor. It features a density of 96 macrocells and supports a maximum clock frequency of 100 MHz with a propagation delay of 10 ns. The device utilizes CMOS technology and includes three dedicated inputs alongside 96 I/O lines. It is housed in a 128-pin Plastic Quad Flat Package (PQFP) or Thin Quad Flat Package (TQFP). The component supports In-System Programming (ISP) via JTAG, allowing for field updates without removal from the circuit board.
Feature Summary
- 96 Macrocell architecture with 3 dedicated inputs and 96 I/O lines
- 10 ns propagation delay supporting up to 100 MHz operation
- In-System Programmability (ISP) capability
- CMOS technology with 5V tolerant I/O options
Applications
- General-purpose logic replacement
- Address decoding and bus bridging
- State machine implementation
- Interface translation between different voltage domains
Procurement Notes
Verify RoHS compliance status as specific suffixes determine environmental certification. Confirm package variant (PQFP vs TQFP) matches PCB footprint requirements. Ensure design tools support legacy EE PLD families for programming and simulation. Check supply chain availability due to potential end-of-life status for older Lattice product lines.
Selection Notes
Select this device when a high pin count (128 pins) is required for extensive I/O expansion within a CPLD architecture. Compare against ispMACH 4000 series if higher performance (up to 400 MHz) or lower power consumption is needed. Consider the ISPLSI2096A or E variants based on specific temperature ranges and packaging preferences.
Part Context
This part belongs to the Lattice ispLSI 2000 family of EE PLDs. These devices were designed to replace complex discrete logic gates and standard PALs/GALs. They offer non-volatile configuration storage, retaining program data when power is removed, which simplifies system boot-up sequences compared to volatile SRAM-based FPGAs.
