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LMG3526R030RQSR is listed in the Power Driver Modules range at ChipApex. The manufacturer field lists Texas Instruments. Its product description is 650-V 30-M GAN FET WITH INTEGRAT. Review the specifications below when checking this part for your BOM.
The LMG3526R030RQSR is a 650V GaN FET with integrated driver, protection, and temperature reporting. It features a 30mΩ on-resistance at 25°C and supports up to 150V/ns slew rate. The device operates from a 7.5V to 18V supply and includes zero-voltage detection (ZVD). Protection mechanisms include cycle-by-cycle overcurrent, latched short-circuit, and self-protection against overtemperature and UVLO. It utilizes a top-side cooled 12mm × 12mm VQFN package.
Verify the specific suffix RQS corresponds to the 52-pin VQFN package configuration. Confirm that the ordering part number matches the exact ZVD-enabled variant required for your design. Ensure compatibility with the recommended operating conditions regarding supply voltage and thermal management requirements specified in the datasheet.
Select this component when zero-voltage switching support is required within a 650V GaN topology. Consider the adjustable slew rate capability for EMI mitigation. Evaluate the thermal resistance metrics for heat dissipation needs. Compare against LMG3527R030 if zero-current detection is preferred instead of zero-voltage detection.
This device belongs to the LMG352xR030 family of integrated GaN FETs. It shares the same core power stage and protection architecture as the LMG3522R030 and LMG3527R030. The primary distinction lies in the detection features: LMG3526R030 provides ZVD, while LMG3527R030 offers ZCD. All variants utilize the same 52-pin VQFN package.
LMG3527R030RQSR
The ZVD pin outputs a pulse signal indicating that zero-voltage switching has been achieved in the current switching cycle.
The slew rate is adjusted by connecting a resistor from the RDRV pin to the SOURCE pin, allowing control between 20V/ns and 150V/ns.
The FAULT pin asserts low during overcurrent, short-circuit, overtemperature, VDD UVLO, or high-impedance RDRV pin conditions.
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