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MC145170DT2 is listed in the Clock Generators, PLLs, Frequency Synthesizers range at ChipApex. The manufacturer field lists NXP USA Inc.. Its product description is IC CLK/FREQ SYNTH 16TSSOP. Review the specifications below when checking this part for your BOM.
The MC145170DT2 is a single-chip PLL frequency synthesizer in a TSSOP-16 package, designed for direct use in MF, HF, and VHF bands. It features fully programmable R (1–32,767) and N (40–65,535) counters with a BitGrabber serial interface requiring no address bits. The device operates on a 2.7 V to 5.5 V supply, drawing up to 5.8 mA at 185 MHz. It includes dual phase detectors with linear transfer functions, an internal oscillator circuit, and a robust power-on reset mechanism.
Verify the DT suffix corresponds to the TSSOP-16 package and check RoHS compliance status, as original documentation indicates non-compliance. Confirm the specific revision (MC145170-2) for the improved power-on reset circuit characteristics before integration.
Select this component when designing synthesizers for frequencies up to 185 MHz with a 5.5 V maximum supply. Ensure the application can accommodate the 2.7 V minimum operating voltage and that the serial interface timing requirements (setup/hold times) are met by the host controller.
This part is the MC145170-2 variant, which is pin-for-pin compatible with the MC145170-1 but features a more robust power-on reset circuit. It draws approximately 20 µA additional quiescent current compared to the previous version while maintaining the same maximum specification limits.
The MC145170-1 is a functional predecessor with identical pinouts but lacks the enhanced POR circuit. No other direct substitutes are documented in the provided source material.
The MC145170-2 has a more robust power-on reset circuit that is more responsive to momentary power supply interruptions, drawing approximately 20 µA more supply current than the MC145170-1.
The jam-load feature initializes both the N and R counters with their respective values simultaneously when a new divide ratio is loaded, reducing lock times and preventing erroneous data loading.
Yes, DC coupling is permitted if the external signal swings rail-to-rail. In this case, OSCout must be left unconnected, and no external feedback resistor is required.
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