MC88915TFN70

Clock Generators, PLLs, Frequency Synthesizers Overview

The MC88915TFN70 is a low skew CMOS PLL clock driver manufactured by NXP USA Inc. (formerly Motorola). It operates at a maximum frequency of 70 MHz for the 2X_Q output and 35 MHz for Q outputs, with a supply voltage range of 4.75V to 5.25V. The device features five phase-locked outputs (Q0–Q4) with less than 500 ps skew, plus inverted (Q5), doubled (2X_Q), and divided (Q/2) variants. Inputs are TTL-compatible, while outputs drive ±36 mA CMOS/TTL loads. Packaged in a 28-lead PLCC, it supports synchronous distribution for high-performance systems.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Phase-Locked Loop (PLL) technology locks multiple outputs to a single reference input with minimal skew (<500 ps between Q0-Q4 rising edges).
• Provides seven distinct output signals: five primary Q outputs, one inverted Q5, one doubled 2X_Q, and one divided Q/2.
• TTL-level compatible inputs with CMOS/TTL output drivers capable of ±36 mA current drive.
• Includes test mode via PLL_EN pin and three-state control via OE/RST pin for board-level testing.

Clock Generators, PLLs, Frequency Synthesizers Applications

• Clock distribution for high-performance personal computers and workstations.
• Synchronous system clock distribution across multiple circuit boards.
• Multiplying low-frequency input clocks to higher local system frequencies.

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify component status as this part number may be discontinued or superseded. Confirm that the 70MHz variant meets specific thermal requirements, as the TFN70 version operates within a 0°C to +70°C temperature range, unlike other versions in the family which support -40°C to +85°C. Ensure compatibility with existing 5V power rails.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select the MC88915TFN70 when a maximum operating frequency of 70 MHz on the 2X_Q output is required. Compare against TFN55 (55 MHz max) or TFN100 (100 MHz max) if frequency needs differ. Note that the TFN70 has a restricted commercial temperature range (0°C to +70°C) compared to industrial versions (-40°C to +85°C). Verify feedback configuration requirements for desired input-to-output frequency ratios.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the MC88915T family of low skew CMOS PLL clock drivers, which includes variants rated for 55, 70, 100, 133, and 160 MHz. The 'FN' suffix indicates a plastic PLCC package (Case 776-02). The device was originally produced by Motorola before being acquired by NXP.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Consider checking for newer iterations within the MC88915T family or consulting manufacturer obsolescence notices for direct replacements.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum operating frequency for the Q outputs?

For the MC88915TFN70, the maximum operating frequency for the Q0–Q4 and Q5 outputs is 35 MHz, while the 2X_Q output can reach up to 70 MHz.

How does the FREQ_SEL pin affect operation?

The FREQ_SEL pin provides a programmable divide-by option in the PLL feedback path. Holding it high selects divide-by-1, while holding it low selects divide-by-2, allowing the VCO to run in its optimal range (>20 MHz) even with lower frequency reference inputs.

What is the purpose of the LOCK output?

The LOCK indicator output goes high when the loop achieves steady-state phase and frequency lock. It goes low if phase-lock is lost or if the PLL_EN pin is pulled low.