MDB1900ZBQY-TR

Overview

The MDB1900ZBQY-TR is a zero-delay clock buffer manufactured by Microchip Technology, originally designed by Micrel. It features a fully integrated programmable PLL for distributing reference clocks in PCIe (Gen1/Gen2/Gen3), SATA, SAS, ESI, and Intel QPI systems. The device accepts differential HCSL input and provides 19 differential HCSL-compatible outputs with a 2:19 ratio. It operates on a 2.375V to 3.465V supply within the -40°C to +85°C temperature range. Key electrical parameters include cycle-to-cycle jitter under 35ps in PLL mode, output-to-output skew under 35ps, and an input-to-output delay variation of 13ps.

Feature Summary

• Supports true zero-delay buffer mode for 100MHz and 133.33MHz frequencies using external feedback.
• Provides 19 differential HCSL-compatible clock output pairs with dedicated OE# pins for glitch-free control.
• Includes an SMBus interface for configuring output properties, enabling/disabling outputs, and selecting from nine addresses.
• Capable of filtering incoming clock jitter and supports spread spectrum modulation for EMI reduction.

Applications

• PCI Express timing distribution for Gen1, Gen2, and Gen3 in Intel platforms.
• SATA and SAS storage system timing.
• Intel Quickpath Interconnect (QPI) applications.
• ESI and SMI system timing.

Procurement Notes

Verify component authenticity as this part was originally manufactured by Micrel before acquisition by Microchip. Confirm the 'QY' suffix indicates the industrial temperature grade (-40°C to +85°C). Check current availability status, as the product may be discontinued or subject to long lead times due to its age. Ensure the package matches the 72-pin 10mm x 10mm QFN specification.

Selection Notes

Select this component when designing systems requiring low-jitter clock distribution for high-speed serial interfaces like PCIe Gen3 or QPI. Ensure the design accommodates the specific external feedback resistor values (e.g., 33Ω series, 49.9Ω shunt for 100Ω impedance) required for zero-delay operation. Verify that the host controller supports the HCSL logic levels and that the SMBus address configuration allows for multiple devices on the same bus if needed.

Part Context

This component corresponds to the Micrel MDB1900ZB, identified by Intel as G20746-002. It is designed to meet Intel's DB1900Z specification. The 'MDB1900ZBQY-TR' designation specifically denotes the tape and reel shipping format for the industrial temperature variant. It belongs to the broader category of application-specific clock and timing buffers used in complex digital systems.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Designers should consult Microchip's official portfolio for newer clock buffer alternatives or verify pin-to-pin compatibility with other zero-delay buffers if sourcing the original Micrel part is not feasible.

FAQ

How is the zero-delay buffer mode achieved?

Zero-delay operation is achieved through an external feedback path connecting the FB_OUT/FB_IN pins. This topology minimizes input-to-output delay variation, which is specified at 13ps in PLL mode.

What are the requirements for the external feedback resistors?

For a 100Ω trace impedance, use a 33Ω series resistor and a 49.9Ω shunt resistor. For an 85Ω trace impedance, use a 27Ω series resistor and a 42.2Ω shunt resistor. These should be placed close to the FB_OUT pins.

Can this device operate with spread spectrum clocking?

Yes, the MDB1900ZB is tolerant of spread spectrum modulation for EMI reduction. It supports modulation frequencies between 30kHz and 33kHz with triangular or Lexmark profiles.