MK2703BSLF

Overview

The MK2703BSLF is a PLL audio clock synthesizer in an 8-pin SOIC package. It accepts a 27 MHz crystal or clock input to generate a buffered reference clock and selectable audio clocks (8.192, 11.2896, 12.288, or 24.576 MHz). The device operates at 3.13 V to 5.5 V with a typical supply current of 10 mA. Key electrical parameters include a maximum absolute jitter of ±150 ps, a duty cycle of 40% to 60%, and zero ppm frequency synthesis error. It utilizes advanced sub-micron CMOS technology.

Feature Summary

• Patented zero ppm synthesis error ensures all output frequencies are frequency locked to the 27 MHz input.
• Selectable audio clock outputs determined by S0 and S1 pin states: 8.192, 11.2896, 12.288, or 24.576 MHz.
• RoHS compliant lead-free packaging in an 8-pin SOIC format.
• Industrial temperature version available (-40°C to +85°C) alongside commercial range.

Applications

• Set-top box systems
• Multimedia systems
• Audio DAC clock generation

Procurement Notes

Verify the specific suffix for the required temperature grade. 'MK2703BSLF' indicates the commercial range (0°C to +70°C), while 'MK2703BSILF' denotes the industrial range (-40°C to +85°C). Confirm RoHS compliance status via the manufacturer's documentation as specifications may change.

Selection Notes

Select based on operating temperature requirements; use MK2703BSLF for commercial applications and MK2703BSILF for industrial environments. Ensure the design accommodates the 27 MHz fundamental mode crystal input and provides appropriate decoupling capacitors (0.01µF) near the VDD pins.

Part Context

The MK2703B series was originally manufactured by Integrated Device Technology (IDT) / ICS. Renesas Electronics Corporation acquired IDT, making Renesas the current manufacturer for this component line. The part is designed to replace discrete oscillators and VCXOs in multimedia applications.

Replacement Considerations

Public confirmed substitute part numbers are not provided in the source material. Verify compatibility with existing board layouts and crystal load capacitance requirements when considering alternatives.

FAQ

How is the audio clock frequency selected?

The audio clock frequency is selected using the S0 and S1 input pins. Connecting these pins to ground (0) or VDD (1) determines the output among 8.192, 11.2896, 12.288, or 24.576 MHz.

What is the maximum absolute jitter specification?

The maximum absolute jitter (short term) is specified as ±150 ps deviation from the mean.

What external components are required for the crystal connection?

A parallel resonant, fundamental mode, AT cut 27 MHz crystal is required. Small capacitors should be connected from X1 and X2 to ground to adjust stray capacitance, calculated as (CL - 16 pF)*2.