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The MPC9351 is a 2.5V and 3.3V compatible, PLL-based clock generator designed for high-performance clock distribution systems. It features nine low-skew LVCMOS outputs capable of frequencies up to 200 MHz with a maximum output skew of 150 ps. The device utilizes a fully differential PLL design to minimize cycle-to-cycle jitter (max 22 ps RMS) and long-term jitter. Outputs are configurable via divide-by-2, 4, or 8 ratios relative to the internal VCO frequency, which operates between 200 MHz and 400 MHz. It supports zero-delay buffer configurations through external feedback and accepts both LVPECL and LVCMOS reference inputs.
Verify package suffix FA corresponds to the 32-lead LQFP (Case 873A-02). Confirm voltage compatibility requirements (2.5V or 3.3V) match system design. Ensure proper power supply filtering on the VCCA pin using an RC filter to isolate analog PLL noise from digital switching noise.
Select based on required output count (up to 9) and frequency range (25–200 MHz). Choose input type (LVPECL PCLK/PCLK or LVCMOS TCLK) according to source clock availability. Consider fanout capabilities; each output can drive one parallel terminated line or two series terminated lines. Ensure VCO frequency stays within 200–400 MHz for stable operation.
Manufactured by Motorola (now Freescale/NXP), the MPC9351 is part of the timing solutions portfolio targeting mid-range to high-performance telecom and networking applications. It serves as a low-skew clock driver and generator, replacing discrete components in complex clock tree designs.
Public confirmed substitute part numbers are not provided in the source material.