MPC9993FA

Overview

The MPC9993 is a PLL clock driver with an Intelligent Dynamic Clock Switch (IDCS) designed for redundant clock tree architectures. It accepts two differential LVPECL input signals and generates five new differential LVPECL outputs: two pairs regenerate the input frequency and phase, while three pairs generate 2x phase-aligned outputs. The device operates on a single 3.3 V supply within a 32-lead LQFP package. It features fully integrated PLL circuitry, LVCMOS control I/O, and continuous monitoring of input clocks to ensure seamless switching between primary and secondary sources.

Feature Summary

• Intelligent Dynamic Clock Switch (IDCS) continuously monitors inputs and switches to a valid source upon failure detection.
• Generates five differential LVPECL output pairs from two differential LVPECL inputs.
• Supports input reference frequencies from 50 MHz to 100 MHz with a VCO range of 800 MHz to 1600 MHz.
• Includes LVCMOS control interfaces with internal pull-up/pull-down resistors for simplified configuration.

Applications

• Redundant clock tree designs requiring high availability.
• Systems needing phase-aligned 1x and 2x clock distribution.
• Applications requiring automatic failover between dual clock sources.

Procurement Notes

Verify the ordering suffix to confirm the package type and lead-free status. The 'FA' suffix denotes a standard 32-lead LQFP package, while the 'AC' suffix indicates a Pb-Free version of the same package. Ensure the specific suffix matches the manufacturing requirements for the target assembly process.

Selection Notes

Select this component when designing systems that require redundant clocking with minimal phase disturbance during switching. Verify that the input clock signals are compatible with LVPECL standards and that the system can accommodate the required 3.3 V power supply. Consider the thermal resistance specifications if operating in environments with limited airflow.

Part Context

Originally manufactured by Freescale Semiconductor, this device is now part of NXP USA Inc.'s portfolio following corporate acquisitions. The datasheet revision is Rev 3, dated June 2005. It belongs to the family of advanced clock drivers designed for robust signal integrity in complex digital systems.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Users should consult official distributor databases or manufacturer cross-reference tools for equivalent components with similar IDCS capabilities and LVPECL output configurations.

FAQ

How does the Intelligent Dynamic Clock Switch (IDCS) handle clock failures?

The IDCS continuously monitors both input CLK signals. Upon detecting a failure, such as a clock stuck HIGH or LOW for at least one period, it latches the bad flag and automatically switches to the good secondary clock, performing phase/frequency alignment with minimal output phase disturbance.

What is the function of the Manual_Override pin?

Asserting Manual_Override HIGH disables the internal clock switch circuitry, allowing the PLL to function normally based on the Sel_Clk selection. Asserting it LOW enables the IDCS mode, allowing automatic switching based on input health.

What are the output frequency capabilities of the MPC9993?

The device supports an input reference frequency of 50 MHz to 100 MHz. The QA outputs provide 1x frequency multiplication, while the QB outputs provide 2x frequency multiplication, resulting in output frequencies up to 200 MHz for QB and 100 MHz for QA.