NB2309AI1HDG

Overview

The NB2309AI1HDG is a 3.3 V zero delay clock buffer manufactured by onsemi, designed to distribute high-speed clocks with low skew. It accepts one reference input and drives nine outputs grouped as four plus four plus one. The device features an internal phase-locked loop (PLL) that locks to the input clock via the CLKOUT feedback pin. Operating within a frequency range of 15 MHz to 133 MHz, it guarantees output-to-output skew of less than 250 ps and cycle-to-cycle jitter under 200 ps. The part operates on a single 3.0 V to 3.6 V supply and is housed in a 16-pin SOIC package.

Feature Summary

• Zero Input-Output Propagation Delay
• Output-to-Output Skew Less Than 250 ps
• Device-to-Device Skew Less Than 700 ps
• Cycle-to-Cycle Jitter Less Than 200 ps

Applications

• CPU Clock Distribution
• PCI Bus Frequency Distribution
• Pentium-Based System Clocking

Procurement Notes

Verify component authenticity through authorized channels. Confirm RoHS compliance status and check for End-of-Life notifications prior to procurement. Ensure packaging specifications match design requirements.

Selection Notes

Select this model for applications requiring a single input to drive multiple synchronized outputs with minimal skew. Verify load capacitance requirements: 30 pF below 100 MHz and 10 pF from 100 MHz to 133 MHz. Ensure all outputs, including CLKOUT, are uniformly loaded to maintain zero delay characteristics.

Part Context

This component belongs to the NB2309A family of 3.3 V zero delay buffers. The -1H suffix indicates a high-drive version with faster rise and fall times compared to standard -1 devices. It utilizes advanced 0.35 µm CMOS technology and supports spread spectrum clock inputs.

Replacement Considerations

NB2309AI1DR2G

FAQ

How is zero input-output delay achieved?

All outputs, including the CLKOUT pin used for internal PLL feedback, must be uniformly loaded with equal capacitive loads.

What is the maximum operating frequency?

The device operates up to 133 MHz.

Can unused outputs be disabled?

Yes, Bank B outputs can be three-stated using the Select inputs when not required.