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The PBRP113ZT is a PNP Resistor-Equipped Transistor (RET) from Nexperia, housed in an SOT23 surface-mounted package. It integrates bias resistors R1 and R2 with values of 1 kΩ and 10 kΩ respectively, yielding a ratio of 10. The device supports a collector-emitter voltage of -40 V and an output current of -600 mA. Key electrical characteristics include a DC current gain (hFE) ranging from 190 to 270 at -50 mA, and a low collector-emitter saturation voltage (VCEsat) as low as -45 mV under specific pulsed conditions. Thermal resistance from junction to ambient is typically 500 K/W in free air.
Verify the ordering suffix matches the required tape and reel configuration for automated assembly. Confirm that the SOT23 footprint aligns with the manufacturer's recommended soldering guidelines to ensure reliable joint formation during reflow or wave soldering processes.
Select this component when a compact PNP solution with integrated base biasing is required. Ensure the application current does not exceed the 600 mA limit and verify that the -40 V rating accommodates the maximum circuit voltage. Consider the thermal derating curves if operating in enclosed environments.
This part belongs to the Performance-Based (PB) RET series, designed to replace discrete transistor and resistor combinations. It serves as the PNP complement to the NPN PBRN113ZT, offering symmetrical design options for push-pull or complementary logic circuits within space-constrained PCB layouts.
Direct functional substitutes include other PNP RETs in SOT23 packages with similar 1k/10k resistor ratios and -40V ratings. Verify pinout compatibility and thermal characteristics before substitution.
The internal bias resistors are R1 = 1 kΩ and R2 = 10 kΩ, resulting in a fixed ratio of 10.
Pin 1 is the Input (Base), Pin 2 is Ground (Emitter), and Pin 3 is Output (Collector).
The typical DC current gain is approximately 270, with a minimum specified value of 190 at IC = -50 mA and VCE = -5 V.