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The Nexperia PDTA114EU is a PNP Resistor-Equipped Transistor (RET) housed in an SOT323 (SC-70) surface-mounted package. It integrates bias resistors R1 and R2, both nominally 10 kΩ, to simplify circuit design. Key electrical parameters include a collector-emitter voltage (VCEO) of -50 V, an output current (IO) of -100 mA, and a maximum power dissipation of 200 mW at 25 °C ambient temperature. The device features a DC current gain (hFE) of 30 at -5 mA and -5 V, with a transition frequency (fT) of 180 MHz.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details such as tape and reel quantities or cut tape availability. Confirm RoHS compliance status and lead times directly with authorized distributors or Nexperia sales offices prior to finalizing procurement plans.
Select this component when a compact PNP switching solution with integrated biasing is required. Ensure the application voltage does not exceed the -50 V collector-emitter rating and that the load current remains within the -100 mA limit. Verify thermal management requirements if operating near the 200 mW power dissipation threshold.
This part belongs to the PDTA114E series of resistor-equipped transistors from Nexperia. It serves as the PNP counterpart to the NPN PDTC114EU. The RET technology combines a bipolar junction transistor with internal biasing resistors into a single small-footprint package, optimizing board space for digital logic and interface circuits.
The NPN complement is the PDTC114EU. For direct functional replacement in PNP configurations, verify equivalent packages like SOT323 and matching electrical ratings. Cross-reference with other manufacturers' RETs offering similar 10kΩ/10kΩ bias ratios and -50V/-100mA specifications.