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The PDTA115TMB is a PNP Resistor-Equipped Transistor (RET) housed in a leadless DFN1006B-3 (SOT883B) package with dimensions of 1.0 x 0.6 x 0.37 mm. It features an integrated input bias resistor R1 of 100 kΩ, while the base-emitter resistor R2 remains open. The device supports a maximum collector-emitter voltage (VCEO) of -50 V and an output current (IO) of -100 mA. Key electrical characteristics include a DC current gain (hFE) of at least 100 at IC = -1 mA, a saturation voltage (VCEsat) of 150 mV max at IC = -5 mA, and a transition frequency (fT) of 180 MHz. It operates within an ambient temperature range of -65 °C to 150 °C and is qualified under AEC-Q101 standards.
Verify the specific ordering suffix '315' against official Nexperia documentation to confirm tape-and-reel packaging specifications. Ensure compatibility with standard surface-mount assembly processes by referencing the provided soldering footprint guidelines for the DFN1006B-3 package. Confirm that the design accounts for the thermal resistance characteristics specified in free-air conditions.
Select this PNP RET when a compact solution is required for general-purpose digital switching or amplification. The internal 100 kΩ resistor simplifies biasing networks compared to discrete transistor configurations. Consider the -50 V rating and 100 mA current limit for appropriate load management. Verify that the open R2 configuration meets the specific interface requirements of the target application.
This component belongs to the PDTA115T series of PNP resistor-equipped transistors. It serves as the PNP complement to the PDTC115TMB NPN variant. Both devices share similar package constraints and functional integration, offering a unified platform for complementary switching designs in mobile and industrial electronics.
The PDTC115TMB is the documented NPN complement within the same series. For direct PNP replacements, verify equivalent packages and electrical ratings such as VCEO and IO against other RET families from Nexperia or alternative manufacturers.