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The PDTB113EUF is a PNP Resistor-Equipped Transistor (RET) manufactured by Nexperia USA Inc. It integrates a PNP transistor with built-in bias resistors in an SOT323 (SC-70) surface-mount package. The device supports a collector-emitter voltage of -50 V and an output current of -500 mA. Key electrical parameters include a DC current gain (hFE) minimum of 33 at -50 mA and -5 V, and a collector-emitter saturation voltage maximum of -100 mV at -50 mA input current. The internal bias network consists of R1 = 1 kΩ and R2 = 1 kΩ, providing a resistor ratio tolerance of ±10%. Thermal characteristics specify a total power dissipation of 300 mW at 25 °C ambient temperature and a junction temperature limit of 175 °C.
Verify the specific ordering suffix 'U' against the manufacturer's latest documentation to confirm tape-and-reel packaging specifications. Confirm that the marking code ZG* matches the intended manufacturing site requirements. Ensure compatibility with standard SOT323 footprints during PCB layout verification.
Select this component when a compact PNP solution with integrated biasing is required for space-constrained designs. Verify that the 1 kΩ resistor values align with the target logic levels and drive currents. Consider the -50 V rating and -500 mA current capability relative to the specific load requirements of the application.
This part belongs to the PDTB1xxxU series of 50 V, 500 mA PNP resistor-equipped transistors. It serves as the PNP complement to the NPN PDTD113EU model within the same family. The series utilizes the SOT323 plastic surface-mounted package to provide a small form factor suitable for modern electronic assemblies.
Public confirmed substitute part numbers: PDTD113EU (NPN complement).