PDTB123YUX

Overview

The PDTB123YUX is a PNP Resistor-Equipped Transistor (RET) housed in a SOT323 (SC-70) surface-mounted plastic package. It features built-in bias resistors with R1 at 2.2 kΩ and R2 at 10 kΩ, yielding a typical resistor ratio of 4.55. The device supports a collector-emitter voltage (VCEO) of -50 V and a continuous output current (IO) of -500 mA. It operates within an ambient temperature range of -55 °C to +175 °C and has a maximum junction temperature of 175 °C. Total power dissipation reaches 300 mW on single-sided copper PCBs and 425 mW on four-layer boards.

Feature Summary

• Built-in bias resistors simplify circuit design and reduce component count
• AEC-Q101 qualified for automotive applications
• High temperature operation capability up to 175 °C

Applications

• Digital applications in automotive and industrial segments
• Controlling IC inputs
• Switching loads
• Cost-saving alternative to BC807 or BC817 series transistors in digital applications

Procurement Notes

Verify the specific ordering suffix against official Nexperia documentation to confirm packaging details such as reel quantity or tape-and-reel specifications. Ensure the procurement channel provides valid traceability and authenticity guarantees for AEC-Q101 qualified components intended for automotive use.

Selection Notes

Select this component when a compact PNP transistor solution with integrated biasing is required for space-constrained designs. The SOT323 package offers a small footprint suitable for high-density PCB layouts. Consider the -50 V rating and 500 mA current capability to ensure adequate headroom for the intended switching or amplification application.

Part Context

This part belongs to the PDTB1xxxU series of 50 V, 500 mA PNP resistor-equipped transistors manufactured by Nexperia. The 'U' suffix specifically denotes the SOT323 (SC-70) plastic surface-mounted package variant within this family.

Replacement Considerations

PDTD123YU is the NPN complement within the same series. For direct functional substitution in PNP configurations, verify pinout compatibility and electrical parameters against other RET families.