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The Nexperia PDTC114EU is an NPN Resistor-Equipped Transistor (RET) housed in a compact SOT323 (SC-70) surface-mounted package. It integrates bias resistors to simplify circuit design and reduce component count. Key electrical parameters include a collector-emitter voltage (VCEO) of 50 V, an output current capability of 100 mA, and a total power dissipation of 200 mW at 25 °C. The internal input resistor (R1) has a typical value of 10 kΩ with a range of 7 to 13 kΩ, while the R2/R1 ratio typically equals 1.
Verify that the specific order suffix matches the required packaging format, such as tape and reel quantities. Confirm the product status aligns with project timelines, noting that this version is non-automotive qualified. Ensure compatibility with standard SC-70 footprints during procurement planning.
Select this component when a small form factor is required alongside integrated biasing. The 10 kΩ input resistance suits general logic interfacing. Verify thermal constraints against the 625 K/W junction-to-ambient rating if operating without PCB copper support.
This device belongs to the NPN Resistor-Equipped Transistor family from Nexperia. It serves as a direct replacement for discrete transistor-resistor networks in space-constrained designs. The SOT323 package provides a compact solution compared to larger through-hole or standard SMD packages.
Check pinout compatibility with existing BC847/857 circuits. Verify that the integrated resistor values meet the specific bias requirements of the target application before substituting.