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The PDTC114TS,126 is an NPN resistor-equipped transistor (RET) from the PDTC114T series, manufactured by Nexperia. It features a built-in input bias resistor (R1) of 10 kΩ with R2 left open. The device is housed in the SOT54 package (SC-43A/TO-92), a plastic single-ended leaded through-hole package with three leads. Key electrical parameters include a collector-emitter voltage (VCEO) of 50 V and an output current capability of 100 mA. The total power dissipation is rated at 500 mW at an ambient temperature of 25 °C. The DC current gain (hFE) is specified as a minimum of 200 at IC = 1 mA and VCE = 5 V.
Verify the ordering suffix '126' against the manufacturer's packing information table. This suffix corresponds to the tape ammopack format for the SOT54 package. Confirm that this specific packaging method aligns with your assembly requirements before procurement.
Select the PDTC114TS variant when a through-hole SOT54 package is required for the PDTC114T series. Ensure the 10 kΩ input resistance meets the base drive requirements. Verify thermal constraints, as the SOT54 package has a junction-to-ambient thermal resistance of 250 K/W.
This component belongs to the PDTC114T family of NPN resistor-equipped transistors. The family includes various packages such as SOT416, SOT346, SOT883, SOT23, and SOT323. The PDTC114TS specifically utilizes the SOT54 through-hole form factor, distinguishing it from the surface-mount variants within the same electrical specification group.
The PDTA114TS is the PNP complement within the same series. Other PDTC114T variants (e.g., PDTC114TT, PDTC114TU) share identical electrical characteristics but differ in package type (SOT23, SOT323). Direct replacement requires matching the package footprint or adapting the PCB layout.
The internal input bias resistor (R1) is 10 kΩ, with a tolerance range of 7 kΩ to 13 kΩ.
No, the PDTC114TS has R2 configured as open.
The maximum collector-emitter voltage (VCEO) with an open base is 50 V.