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The PDTC114YTVL is an NPN Resistor-Equipped Transistor (RET) manufactured by Nexperia USA Inc. in a SOT23 surface-mounted package. It integrates bias resistors with nominal values of R1 = 10 kΩ and R2 = 47 kΩ. The device supports a collector-emitter voltage (VCEO) of 50 V and an output current (IO) of 100 mA. Key electrical characteristics include a DC current gain (hFE) of 100 at IC = 5 mA, a transition frequency (fT) of 230 MHz, and a maximum total power dissipation of 250 mW.
Verify the specific ordering suffix 'TVL' against official Nexperia documentation to confirm tape-and-reel specifications and manufacturing site codes. Ensure compliance with RoHS directives and verify that the non-automotive qualification status aligns with the intended application environment before procurement.
Select this component when a compact NPN transistor with integrated base biasing is required for industrial digital logic. Compare the 10 kΩ input resistance and 47 kΩ emitter resistor values against circuit requirements. Consider the SOT23 footprint constraints and thermal derating curves for PCB layout optimization.
This part belongs to the Nexperia PDTC114 family of NPN resistor-equipped transistors. It serves as the complement to the PDTA114YT PNP RET. The product data sheet supersedes previous family documents, providing specific single-type characterization for the PDTC114YT variant within the SOT23 package.
Publicly confirmed substitute part numbers are not available in the provided datasheet. Designers should consult Nexperia's official cross-reference tools or distributor databases for equivalent components matching the 50 V, 100 mA, SOT23 RET specification.