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The PDTC115TU,115 is an NPN resistor-equipped transistor (RET) housed in a SOT323 (SC-70) surface-mounted plastic package. It integrates a single internal bias resistor (R1) with the collector-base open configuration. Key electrical parameters include a maximum collector-emitter voltage (VCEO) of 50 V and a continuous DC output current (IO) of 100 mA. The typical input bias resistance (R1) is 100 kΩ, with a specified range from 70 kΩ to 130 kΩ. The device supports a total power dissipation of 200 mW at 25 °C ambient temperature and operates within a junction temperature range up to 150 °C.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm the exact packing method and quantity. Confirm compliance with RoHS and REACH regulations as stated in the product data sheet before finalizing procurement specifications.
Select this component when a compact NPN solution with integrated base biasing is required. Ensure the application voltage does not exceed the 50 V collector-emitter rating and that the thermal environment allows for adequate power dissipation within the SOT323 package constraints.
This part belongs to the PDTC115T series of NPN resistor-equipped transistors manufactured by Nexperia. The series includes various package options such as SOT416, SOT346, SOT883, SOT54, and SOT23, all sharing the same electrical characteristics but differing in physical footprint and mounting style.
PDTC115TE,115
The internal bias resistor (R1) has a typical value of 100 kΩ, with a minimum of 70 kΩ and a maximum of 130 kΩ.
No, the PDTC115TU features an open collector-base configuration with only the input bias resistor (R1) integrated; R2 is open.
The maximum storage temperature (Tstg) for the PDTC115TU is +150 °C.