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The PDTC123TM-QYL is an NPN Resistor-Equipped Transistor (RET) from Nexperia, designed for digital switching applications. It integrates a single base resistor (R1) within the package to simplify circuit design and reduce component count. The device features a maximum collector-emitter voltage of 50 V and a continuous collector current of 100 mA. It is housed in a compact DFN1006B-3 surface-mount package, suitable for space-constrained designs. The part is qualified under AEC-Q101 standards, ensuring reliability for automotive environments. Key electrical parameters include a DC current gain (hFE) minimum of 30 at specified test conditions and a low saturation voltage.
Verify the specific suffix -QYL against official Nexperia documentation to confirm AEC-Q101 qualification status and exact pinout configuration. Ensure compatibility with existing footprint designs, as the DFN1006B-3 package dimensions differ from standard SOT packages. Cross-reference ordering codes with authorized distributors to avoid counterfeit components.
Select this component when a small form factor and integrated biasing are required for NPN switching tasks. Compare against the PDTC123TMB series for similar functionality but verify if the specific Q-series automotive qualification is necessary for the target application. Consider thermal dissipation requirements relative to the DFN package's power handling capabilities.
This part belongs to the PDTC123 family of NPN resistor-equipped transistors. It serves as the automotive-grade variant within the broader PDTC123 product line, which includes various package options like SOT23 and SC-70. The TM suffix indicates the DFN1006B-3 package type, distinguishing it from other physical configurations in the same electrical family.
Direct substitutes include the PDTC123TMB series for equivalent electrical performance in non-automotive contexts. For automotive replacements, verify availability of other PDTC123 variants with AEC-Q101 certification. Ensure any replacement maintains the same R1 value and package footprint to preserve board layout integrity.