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The PDTD113ES,126 is an NPN Resistor-Equipped Transistor (RET) from the PDTD113E series, manufactured by Nexperia. It features a built-in bias resistor configuration with R1 = 1 kΩ and R2 = 1 kΩ. The device supports a maximum collector-emitter voltage of 50 V and a continuous output current of 500 mA. It utilizes the SOT54 package (SC-43A/TO-92), which is a plastic single-ended leaded through-hole package. The suffix ,126 indicates tape ammopack packing for wide pitch leads.
Verify the ordering code matches PDTD113ES,126 to confirm the specific SOT54 package variant and tape ammopack packing method. Confirm that the supplier provides the original manufacturer's documentation to ensure compliance with the specified electrical characteristics and marking codes.
Select this component when a through-hole NPN transistor with integrated base and emitter biasing is required. The 1 kΩ input resistance is suitable for standard logic interface applications. Ensure the PCB footprint accommodates the SC-43A/TO-92 lead spacing and verify thermal dissipation requirements against the 500 mW limit.
This part belongs to the PDTD113E series of NPN resistor-equipped transistors. It shares electrical specifications with surface-mount variants like the PDTD113ET but differs in physical packaging. The PDTD113ES specifically targets through-hole assembly needs within the same functional family.
Direct replacements include other PDTD113E series parts such as PDTD113EK or PDTD113ET if package adaptation is possible. Complementary PNP versions are available as PDTB113ES.