SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The PDTD113ZUF is an NPN Resistor-Equipped Transistor (RET) from the PDTD1xxxU series, manufactured by Nexperia USA Inc. It integrates a transistor with built-in bias resistors in a SOT323 (SC-70) surface-mount package. Key electrical parameters include a collector-emitter voltage of 50 V and an output current capability of 500 mA. The device features a 1 kΩ input bias resistor (R1) and a 10 kΩ base-emitter bias resistor (R2). It offers a DC current gain (hFE) of at least 70 at 50 mA and 5 V, with a maximum collector-emitter saturation voltage of 100 mV under specified conditions.
Verify the specific suffix 'F' against official Nexperia documentation to confirm tape and reel packaging details, as datasheets may list standard bulk or cut tape options. Ensure the ordering code matches the required quantity format. Confirm RoHS compliance status and manufacturing origin codes via the latest product data sheet before finalizing procurement orders.
Select this component when a compact NPN switching solution with integrated biasing is required. The PDTD113ZUF variant specifically provides a 1 kΩ input resistor and a 10 kΩ base-emitter resistor, suitable for driving logic outputs directly. Consider the SOT323 package size constraints and the 50 V voltage rating relative to the application's supply voltage and load requirements.
This part belongs to the PDTD1xxxU series of NPN resistor-equipped transistors. It is complemented by the PDTB113ZU PNP counterpart. The series shares common thermal characteristics and package dimensions but varies in internal resistor values. The 'ZU' designation indicates specific resistor ratios within the SC-70 footprint family.
Direct functional substitutes within the same series include PDTD113EU, which shares identical pinout and general specifications but differs in internal resistor configurations. Verify compatibility with existing PCB footprints and ensure that the alternative part's resistor values meet the specific biasing requirements of the target circuit design.