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The PDTD114ETR is an NPN Resistor-Equipped Transistor (RET) manufactured by Nexperia USA Inc. in a SOT23 (TO-236AB) surface-mount package. It integrates bias resistors R1 and R2, both typically 10 kΩ, with a ratio tolerance of ±10%. The device supports a collector-emitter voltage (VCEO) of 50 V and a continuous output current (IO) of 500 mA. Key electrical characteristics include a DC current gain (hFE) minimum of 70 at 50 mA, a transition frequency (fT) of 225 MHz, and a total power dissipation of 320 mW at 25 °C ambient temperature. It operates within a junction temperature range up to 175 °C and holds AEC-Q101 qualification.
Verify the specific ordering suffix against the manufacturer's official documentation to confirm packaging details such as reel or cut tape specifications. Ensure the part number matches the required SOT23 package variant. Confirm AEC-Q101 qualification status if automotive grade compliance is mandatory for the target application environment.
Select this component when a compact NPN solution with integrated biasing is required for space-constrained designs. The 500 mA current capability and 50 V rating suit general switching tasks. Consider the thermal resistance values for PCB layout planning to ensure operation remains within the 175 °C junction temperature limit under expected load conditions.
This device belongs to the NPN Resistor-Equipped Transistor family from Nexperia. It serves as the NPN counterpart to the PDTB114ET PNP RET. Both share similar internal resistor configurations but differ in transistor polarity. The family is designed to replace discrete resistor-transistor combinations in digital logic and interface circuits.
PDTB114ET (PNP complement)
The typical value for both R1 (input) and R2 is 10 kΩ.
Yes, the PDTD114ET is qualified in accordance with the AEC-Q101 standard for discrete semiconductors.
The maximum collector-emitter voltage (VCEO) is 50 V.