PI6CB33402ZHIEX

Clock Buffers, Drivers Overview

The PI6CB33402 is a very low power 4-output PCIe clock buffer manufactured by Diodes Incorporated. It accepts a differential HCSL input and provides four low-power differential HCSL outputs with integrated on-chip termination, eliminating the need for external resistors. The device operates at a nominal 3.3V supply voltage and supports frequencies of 100MHz, 50MHz, 125MHz, and 133.33MHz via SMBus configuration. It features a proprietary PLL design to achieve very low jitter compliant with PCIe Gen 1 through Gen 5 standards. Key specifications include a maximum output frequency of 133.33MHz, an operating temperature range of -40°C to +85°C, and a 32-contact TQFN package.

Clock Buffers, Drivers Feature Summary

• Four differential low-power HCSL outputs with on-chip termination (default ZOUT = 85Ω).
• Supports 100MHz default operation; programmable to 50MHz, 125MHz, or 133.33MHz via SMBus.
• Very low jitter performance: Differential cycle-to-cycle jitter <50ps in PLL mode.
• Individual output enable pins (OE0#-OE3#) for granular power management.

Clock Buffers, Drivers Applications

• PCIe Gen 1/Gen 2/Gen 3/Gen 4/Gen 5 clock distribution.
• Ethernet applications requiring 50MHz, 125MHz, or 133.33MHz clock signals.
• High-speed digital systems requiring low-jitter clock buffering.

Clock Buffers, Drivers Procurement Notes

Verify the specific ordering suffix against the datasheet to confirm tape orientation. The part number PI6CB33402ZHIEX corresponds to the 32-contact TQFN package with Pin 1 located at the top right corner. Ensure that the procurement documentation matches the required package code ZH and confirms RoHS compliance and lead-free status as specified by the manufacturer.

Clock Buffers, Drivers Selection Notes

Select this component when a 1:4 fanout buffer with integrated termination is required to simplify PCB layout. It is suitable for designs needing support for multiple standard frequencies (50MHz, 100MHz, 125MHz, 133.33MHz) without external crystal changes. Consider the SMBus interface requirements for dynamic configuration of slew rate, amplitude, and PLL bandwidth if adaptive performance tuning is necessary for the target application.

Clock Buffers, Drivers Part Context

This device belongs to the PI6CB33 series of clock buffers from Diodes Incorporated. It is designed to replace discrete resistor networks for HCSL termination, reducing component count and board space. The integration of the PLL allows for jitter cleaning and frequency multiplication/division capabilities within a single small footprint package.

Clock Buffers, Drivers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided source material.

Clock Buffers, Drivers FAQ

What is the default output impedance of the on-chip termination?

The default on-chip termination impedance (ZOUT) is 85Ω.

How is the SMBus address configured?

The SMBus address is latched on the SADR_TRI pin upon the first high assertion of the PD# pin. The address can be selected using tri-level latching states.

Can the device operate in bypass mode?

Yes, the PLL operating mode can be set to bypass via the BW_SEL_TRI pin or SMBus. In bypass mode, the PLL is off, and inputs pass directly to the outputs.