PI6CG33401CZHIEX-13R

Clock Generators, PLLs, Frequency Synthesizers Overview

The PI6CG33401C is a 4-output very-low-power PCIe clock generator designed for Gen1 through Gen6 applications. It accepts a 25MHz crystal or CMOS reference input to generate four differential low-power HCSL outputs at 100MHz, featuring integrated on-chip termination with a default impedance of 100Ω. The device operates on a single 3.3V supply (3.135V to 3.465V) and includes an additional buffered CMOS reference output. Key electrical parameters include a maximum operating temperature of 85°C, cycle-to-cycle jitter under 50ps, and output skew less than 50ps. Configuration is managed via strapping pins or SMBus.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates four differential low-power HCSL outputs with built-in on-chip termination to reduce external component count.
• Supports selectable spread-spectrum options of 0%, -0.25%, or -0.5% to minimize electromagnetic interference.
• Provides individual output enable control and programmable slew rate and amplitude settings for each output channel.
• Includes a buffered CMOS reference output serving as a low-noise reference source for other circuitry.

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCIe Gen1/Gen2/Gen3/Gen4/Gen5/Gen6 common clock architectures
• High-speed data transmission systems requiring low-jitter clocking
• Servers and storage devices needing optimized board performance

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against manufacturer documentation to confirm package orientation and pinout details. Ensure that configuration requirements such as spread spectrum selection and output enable states align with the hardware strapping pin definitions provided in the datasheet before finalizing procurement specifications.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when designing systems requiring compliance with PCIe Gen1 through Gen6 jitter specifications. Consider the integrated termination feature if layout complexity reduction is a priority. Verify that the 25MHz input frequency requirement matches the system's available reference sources and that the 3.3V supply voltage range accommodates the target power delivery network.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the PI6CG334 series of clock generators from Diodes Incorporated. It shares functional similarities with models like the PI6CG33402 but differs in specific output configurations and internal parameter settings. The series is characterized by its proprietary PLL design aimed at achieving ultra-low jitter performance suitable for high-speed serial interfaces.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct substitutes within the same family include the PI6CG33402CZHIEX. When replacing, verify that the pinout compatibility remains consistent and that the replacement part supports the required PCIe generation standards and jitter performance metrics specified in the original design.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How is the SMBus address determined for the PI6CG33401C?

The SMBus address is latched based on the state of the SADR pin upon the first assertion of the PD# pin. A logic low sets the address to 1101000, while a logic high sets it to 1101010.

What happens to the differential outputs before the PLL locks?

The differential outputs are blocked until the Phase-Locked Loop (PLL) achieves lock. This ensures stable clock signals are only presented to downstream components once the frequency and phase are stabilized.

Can the spread spectrum amount be changed after power-up?

No, the spread spectrum amount must be selected using the SS_SEL_TRI pin at initial power-up. While the SMBus can modify the spread amount if software control is enabled, it cannot turn the spread spectrum on or off after power-up without resetting the system.